Merge branch 'YosysHQ:main' into main

tests/cxxrtl/run-test.sh

@@ -13,5 +13,5 @@ run_subtest value
 run_subtest value_fuzz
 
 # Compile-only test.
-../../yosys -p "read_verilog test_unconnected_output.v; select =*; proc; clean; write_cxxrtl cxxrtl-test-unconnected_output.cc"
+../../yosys -p "read_verilog test_unconnected_output.v; proc; clean; write_cxxrtl cxxrtl-test-unconnected_output.cc"
 ${CC:-gcc} -std=c++11 -c -o cxxrtl-test-unconnected_output -I../../backends/cxxrtl/runtime cxxrtl-test-unconnected_output.cc

tests/liberty/libcache.ys

@@ -0,0 +1,58 @@
+libcache -enable busdef.lib
+
+logger -expect log "Caching is disabled by default." 1
+logger -expect log "Caching is enabled for `busdef.lib'." 1
+libcache -list
+logger -check-expected
+
+logger -expect log "Caching data" 1
+log Caching data
+read_liberty normal.lib; design -reset
+logger -check-expected
+
+logger -expect log "Caching data" 1
+read_liberty -lib busdef.lib; design -reset
+logger -check-expected
+
+logger -expect log "Using caching data" 1
+log Using caching data
+read_liberty normal.lib; design -reset
+logger -check-expected
+
+logger -expect log "Using cached data" 1
+read_liberty -lib busdef.lib; design -reset
+logger -check-expected
+
+libcache -purge busdef.lib
+
+logger -expect log "Caching is disabled by default." 1
+logger -expect log "Caching is enabled for `busdef.lib'." 1
+log Caching is enabled for `busdef.lib'.
+libcache -list
+logger -check-expected
+
+libcache -enable -all
+
+logger -expect log "Caching is enabled by default." 1
+libcache -list
+logger -check-expected
+
+logger -expect log "Caching data" 1
+read_liberty normal.lib; design -reset
+logger -check-expected
+
+logger -expect log "Caching data" 1
+read_liberty -lib busdef.lib; design -reset
+logger -check-expected
+
+logger -expect log "Using cached data" 1
+read_liberty -lib busdef.lib; design -reset
+logger -check-expected
+
+logger -expect log "Using cached data" 1
+read_liberty normal.lib; design -reset
+logger -check-expected
+
+logger -expect log "Using cached data" 1
+dfflibmap -liberty normal.lib
+logger -check-expected

tests/select/blackboxes.ys

@@ -1,3 +1,4 @@
+read_verilog -specify <<EOT
 module top(input a, b, output o);
 assign o = a & b;
 endmodule
@@ -14,3 +15,14 @@ endmodule
 module wb(input a, b, output o);
 assign o = a ^ b;
 endmodule
+EOT
+clean
+
+select -assert-count 1 c:*
+select -assert-none t:* t:$and %d
+select -assert-count 3 w:*
+select -assert-count 4 *
+
+select -assert-count 3 =c:*
+select -assert-count 10 =w:*
+select -assert-count 13 =*

tests/select/boxes_equals_clean.ys

@@ -1,7 +0,0 @@
-read_verilog -specify boxes.v
-clean
-
-logger -expect-no-warnings
-select -assert-count 5 =wb
-clean =wb
-select -assert-count 4 =wb

tests/select/boxes_equals_name.ys

@@ -1,7 +0,0 @@
-read_verilog -specify boxes.v
-clean
-
-select -set top top
-select -assert-count 4 @top
-select -set boxes =?b
-select -assert-count 9 @boxes

tests/select/boxes_equals_operators.ys

@@ -1,38 +0,0 @@
-read_verilog -specify boxes.v
-clean
-
-# wb = 4w1c, bb = 3w1c, top = 3w1c
-select =wb
-select -assert-count 5 %
-select -add =bb
-select -assert-count 9 %
-select -del =wb
-select -assert-count 4 %
-
-# unions
-select -assert-count 8 =bb * %u
-select -assert-count 8 * =bb %u
-select -assert-count 13 top =* %u
-select -assert-count 8 =bb top %u
-select -assert-count 8 top =bb %u
-
-# intersections
-select -assert-count 3 =w:* =bb %i
-select -assert-count 4 =* * %i
-select -assert-count 4 * =* %i
-
-# inverses
-select -assert-count 8 =wb %n
-select -assert-none top %n
-select -assert-none * %n
-select -assert-none =* %n
-select -assert-count 9 =top %n
-
-# differences
-select -assert-count 9 =* top %d
-select -assert-count 0 top =* %d
-select -assert-count 9 =* * %d
-select -assert-count 0 * =* %d
-
-# random
-select -assert-any =?b %R

tests/select/boxes_equals_pattern.ys

@@ -1,7 +0,0 @@
-read_verilog -specify boxes.v
-clean
-
-select -assert-none ?b
-select -assert-count 4 =bb
-select -assert-count 5 =wb
-select -assert-count 9 =?b

tests/select/boxes_equals_wildcard.ys

@@ -1,6 +0,0 @@
-read_verilog -specify boxes.v
-clean
-
-select -assert-count 3 =c:*
-select -assert-count 10 =w:*
-select -assert-count 13 =*

tests/select/boxes_no_equals.ys

@@ -1,7 +0,0 @@
-read_verilog -specify boxes.v
-clean
-
-select -assert-count 1 c:*
-select -assert-none t:* t:$and %d
-select -assert-count 3 w:*
-select -assert-count 4 *

tests/select/boxes_no_equals_clean.ys

@@ -1,18 +0,0 @@
-read_verilog -specify boxes.v
-
-logger -expect warning "did not match any module" 2
-clean wb
-opt_clean wb
-logger -check-expected
-
-select -clear
-logger -expect warning "did not match any module" 2
-clean wb
-opt_clean wb
-logger -check-expected
-
-select -none
-logger -expect warning "did not match any module" 2
-clean wb
-opt_clean wb
-logger -check-expected

tests/select/boxes_stack.ys

@@ -1,29 +0,0 @@
-read_verilog -specify boxes.v
-clean
-
-# default selection == select *
-select -assert-count 4 *
-select -assert-count 4 %
-
-# -none replaces default selection
-select -none
-select -assert-none %
-select -assert-count 13 =*
-
-# select replaces current selection
-select =*
-select -assert-count 13 %
-
-# -module changes module
-select -module wb
-select -assert-none %
-select -assert-count 5 =*
-
-# -none maintains module
-select -none
-select -assert-count 5 =*
-
-# -clear clears current selection and module
-select -clear
-select -assert-count 4 %
-select -assert-count 13 =*

tests/simple_abc9/run-test.sh

@@ -49,6 +49,6 @@ exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v *.sv EXTRA_FLAGS="-f \"veri
     clean; \
     check -assert * abc9_test037 %d; \
     select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%; \
-    setattr -mod -unset blackbox -unset whitebox =*'"
+    setattr -mod -unset blackbox -unset whitebox'"
 
 # NOTE: Skip 'check -assert' on abc9_test037 because it intentionally has a combinatorial loop