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ilang, ast: Store parameter order and default value information.

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Fixes #1819, #1820.
This commit is contained in:
Marcelina Kościelnicka 2020-04-16 15:51:03 +02:00
parent 79efaa65ad
commit 06a344efcb
6 changed files with 27 additions and 9 deletions
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12
backends/ilang/ilang_backend.cc
View file

@ -290,8 +290,16 @@ void ILANG_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu
if (!module->avail_parameters.empty()) {
if (only_selected)
f << stringf("\n");
for (auto &p : module->avail_parameters)
f << stringf("%s" " parameter %s\n", indent.c_str(), p.c_str());
for (const auto &p : module->avail_parameters) {
const auto &it = module->parameter_default_values.find(p);
if (it == module->parameter_default_values.end()) {
f << stringf("%s" " parameter %s\n", indent.c_str(), p.c_str());
} else {
f << stringf("%s" " parameter %s ", indent.c_str(), p.c_str());
dump_const(f, it->second);
f << stringf("\n");
}
}
}
}

2
frontends/ast/ast.cc
View file

@ -1074,8 +1074,6 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
if (child->type == AST_WIRE && (child->is_input || child->is_output)) {
new_children.push_back(child);
} else if (child->type == AST_PARAMETER) {
child->delete_children();
child->children.push_back(AstNode::mkconst_int(0, false, 0));
new_children.push_back(child);
} else if (child->type == AST_CELL && child->children.size() > 0 && child->children[0]->type == AST_CELLTYPE &&
(child->children[0]->str == "$specify2" || child->children[0]->str == "$specify3" || child->children[0]->str == "$specrule")) {

5
frontends/ast/genrtlil.cc
View file

@ -1015,7 +1015,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// remember the parameter, needed for example in techmap
case AST_PARAMETER:
current_module->avail_parameters.insert(str);
current_module->avail_parameters(str);
if (GetSize(children) >= 1 && children[0]->type == AST_CONSTANT) {
current_module->parameter_default_values[str] = children[0]->asParaConst();
}
/* fall through */
case AST_LOCALPARAM:
if (flag_pwires)

11
frontends/ilang/ilang_parser.y
View file

@ -143,11 +143,18 @@ module_body:
/* empty */;
module_stmt:
param_stmt | attr_stmt | wire_stmt | memory_stmt | cell_stmt | proc_stmt | conn_stmt;
param_stmt | param_defval_stmt | attr_stmt | wire_stmt | memory_stmt | cell_stmt | proc_stmt | conn_stmt;
param_stmt:
TOK_PARAMETER TOK_ID EOL {
current_module->avail_parameters.insert($2);
current_module->avail_parameters($2);
free($2);
};
param_defval_stmt:
TOK_PARAMETER TOK_ID constant EOL {
current_module->avail_parameters($2);
current_module->parameter_default_values[$2] = *$3;
free($2);
};

3
kernel/rtlil.cc
View file

@ -1389,7 +1389,7 @@ void RTLIL::Module::sort()
{
wires_.sort(sort_by_id_str());
cells_.sort(sort_by_id_str());
avail_parameters.sort(sort_by_id_str());
parameter_default_values.sort(sort_by_id_str());
memories.sort(sort_by_id_str());
processes.sort(sort_by_id_str());
for (auto &it : cells_)
@ -1508,6 +1508,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
log_assert(new_mod->refcount_cells_ == 0);
new_mod->avail_parameters = avail_parameters;
new_mod->parameter_default_values = parameter_default_values;
for (auto &conn : connections_)
new_mod->connect(conn);

3
kernel/rtlil.h
View file

@ -1091,7 +1091,8 @@ public:
std::vector<RTLIL::SigSig> connections_;
RTLIL::IdString name;
pool<RTLIL::IdString> avail_parameters;
idict<RTLIL::IdString> avail_parameters;
dict<RTLIL::IdString, RTLIL::Const> parameter_default_values;
dict<RTLIL::IdString, RTLIL::Memory*> memories;
dict<RTLIL::IdString, RTLIL::Process*> processes;