3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 09:05:32 +00:00

ilang, ast: Store parameter order and default value information.

Fixes #1819, #1820.
This commit is contained in:
Marcelina Kościelnicka 2020-04-16 15:51:03 +02:00
parent 79efaa65ad
commit 06a344efcb
6 changed files with 27 additions and 9 deletions

View file

@ -1389,7 +1389,7 @@ void RTLIL::Module::sort()
{
wires_.sort(sort_by_id_str());
cells_.sort(sort_by_id_str());
avail_parameters.sort(sort_by_id_str());
parameter_default_values.sort(sort_by_id_str());
memories.sort(sort_by_id_str());
processes.sort(sort_by_id_str());
for (auto &it : cells_)
@ -1508,6 +1508,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
log_assert(new_mod->refcount_cells_ == 0);
new_mod->avail_parameters = avail_parameters;
new_mod->parameter_default_values = parameter_default_values;
for (auto &conn : connections_)
new_mod->connect(conn);

View file

@ -1091,7 +1091,8 @@ public:
std::vector<RTLIL::SigSig> connections_;
RTLIL::IdString name;
pool<RTLIL::IdString> avail_parameters;
idict<RTLIL::IdString> avail_parameters;
dict<RTLIL::IdString, RTLIL::Const> parameter_default_values;
dict<RTLIL::IdString, RTLIL::Memory*> memories;
dict<RTLIL::IdString, RTLIL::Process*> processes;