3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-24 13:18:56 +00:00

ilang, ast: Store parameter order and default value information.

Fixes #1819, #1820.
This commit is contained in:
Marcelina Kościelnicka 2020-04-16 15:51:03 +02:00
parent 79efaa65ad
commit 06a344efcb
6 changed files with 27 additions and 9 deletions

View file

@ -1074,8 +1074,6 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
if (child->type == AST_WIRE && (child->is_input || child->is_output)) {
new_children.push_back(child);
} else if (child->type == AST_PARAMETER) {
child->delete_children();
child->children.push_back(AstNode::mkconst_int(0, false, 0));
new_children.push_back(child);
} else if (child->type == AST_CELL && child->children.size() > 0 && child->children[0]->type == AST_CELLTYPE &&
(child->children[0]->str == "$specify2" || child->children[0]->str == "$specify3" || child->children[0]->str == "$specrule")) {

View file

@ -1015,7 +1015,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// remember the parameter, needed for example in techmap
case AST_PARAMETER:
current_module->avail_parameters.insert(str);
current_module->avail_parameters(str);
if (GetSize(children) >= 1 && children[0]->type == AST_CONSTANT) {
current_module->parameter_default_values[str] = children[0]->asParaConst();
}
/* fall through */
case AST_LOCALPARAM:
if (flag_pwires)