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Pack hi and lo registers separately

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This commit is contained in:
Eddie Hung 2019-07-22 16:12:57 -07:00
parent 8c31441ba0
commit 068617f094
2 changed files with 70 additions and 39 deletions
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62
passes/pmgen/ice40_dsp.pmg
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@ -60,11 +60,13 @@ match ffH
optional
endmatch
code sigH clock clock_pol
code sigH sigO clock clock_pol
sigH = port(mul, \Y);
sigO = sigH;
if (ffH) {
sigH = port(ffH, \Q);
sigO = sigH;
SigBit c = port(ffH, \CLK).as_bit();
bool cp = param(ffH, \CLK_POLARITY).as_bool();
@ -95,12 +97,10 @@ endmatch
code addAB sigO sigO_signed
if (addA) {
addAB = addA;
sigO = port(addAB, \B);
sigO_signed = param(addAB, \B_SIGNED).as_bool();
}
if (addB) {
addAB = addB;
sigO = port(addAB, \A);
sigO_signed = param(addAB, \A_SIGNED).as_bool();
}
if (addAB) {
@ -112,6 +112,8 @@ code addAB sigO sigO_signed
reject;
if ((actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool()))
reject;
sigO = port(addAB, \Y);
}
endcode
@ -132,36 +134,58 @@ match muxB
optional
endmatch
code muxAB
code muxAB sigO
muxAB = addAB;
if (muxA)
muxAB = muxA;
if (muxB)
muxAB = muxB;
if (muxA || muxB)
sigO = port(muxAB, \Y);
endcode
match ffO
if muxAB
select ffO->type.in($dff)
filter nusers(port(muxAB, \Y)) == 2
filter includes(port(ffO, \D).to_sigbit_set(), port(muxAB, \Y).to_sigbit_set())
match ffO_lo
select ffO_lo->type.in($dff)
filter nusers(sigO.extract(0,16)) == 2
filter includes(port(ffO_lo, \D).to_sigbit_set(), sigO.extract(0,16).to_sigbit_set())
optional
endmatch
match ffO_hi
select ffO_hi->type.in($dff)
filter nusers(sigO.extract(16,16)) == 2
filter includes(port(ffO_hi, \D).to_sigbit_set(), sigO.extract(16,16).to_sigbit_set())
optional
endmatch
code clock clock_pol sigO
if (ffO) {
SigBit c = port(ffO, \CLK).as_bit();
bool cp = param(ffO, \CLK_POLARITY).as_bool();
if (ffO_lo || ffO_hi) {
if (ffO_lo) {
SigBit c = port(ffO_lo, \CLK).as_bit();
bool cp = param(ffO_lo, \CLK_POLARITY).as_bool();
if (port(ffO, \Q) != sigO) {
sigO = port(muxAB, \Y);
sigO.replace(port(ffO, \D), port(ffO, \Q));
if (clock != SigBit() && (c != clock || cp != clock_pol))
reject;
clock = c;
clock_pol = cp;
if (port(ffO_lo, \Q) != sigO.extract(0,16))
sigO.replace(port(ffO_lo, \D), port(ffO_lo, \Q));
}
if (clock != SigBit() && (c != clock || cp != clock_pol))
reject;
if (ffO_hi) {
SigBit c = port(ffO_hi, \CLK).as_bit();
bool cp = param(ffO_hi, \CLK_POLARITY).as_bool();
clock = c;
clock_pol = cp;
if (clock != SigBit() && (c != clock || cp != clock_pol))
reject;
clock = c;
clock_pol = cp;
if (port(ffO_hi, \Q) != sigO.extract(16,16))
sigO.replace(port(ffO_hi, \D), port(ffO_hi, \Q));
}
}
endcode