diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 5328ad404..d2cea3599 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -674,56 +674,61 @@ struct VerilogDefines : public Pass { } } VerilogDefines; -struct VerilogFilelist : public Pass { - VerilogFilelist() : Pass("verilog_filelist", "use filelist") {} +struct VerilogFileList : public Pass { + VerilogFileList() : Pass("read_verilog_file_list", "Parse a Verilog file list") {} void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" verilog_filelist [options]\n"); + log(" read_verilog_file_list [options]\n"); log("\n"); - log("Load a Verilog file list, and pass list of Verilog files to read_verilog command.\n"); + log("Parse a Verilog file list, and pass the list of Verilog files to read_verilog command.\n"); log("\n"); - log(" -Fflist\n"); - log(" File list file contains list of Verilog to be parsed, any\n"); - log(" ' path is relative to the file list file'\n"); + log(" -F file_list_path\n"); + log(" File list file contains list of Verilog files to be parsed, any\n"); + log(" ' path is treated relative to the file list file'\n"); log("\n"); - log(" -Fflist\n"); - log(" File list file contains list of Verilog to be parsed, any\n"); - log(" ' path is relative to current working directroy'\n"); + log(" -f file_list_path\n"); + log(" File list file contains list of Verilog files to be parsed, any\n"); + log(" ' path is treated relative to current working directroy'\n"); log("\n"); } - void parse_flist_rel_filelist(const std::string &flist_path, RTLIL::Design *design) + void parse_file_list(const std::string &file_list_path, RTLIL::Design *design, bool relative_to_file_list_path) { - std::ifstream ifs(flist_path); - if (!ifs.is_open()) { - log_error("file list file does not exist"); + std::ifstream flist(file_list_path); + if (!flist.is_open()) { + log_error("Verilog file list file does not exist"); exit(1); } - std::filesystem::path flist_parent_dir = std::filesystem::path(flist_path).parent_path(); + std::filesystem::path file_list_parent_dir = std::filesystem::path(file_list_path).parent_path(); std::string v_file_name; - while (std::getline(ifs, v_file_name)) { + while (std::getline(flist, v_file_name)) { if (v_file_name.empty()) { continue; } - std::string v_file_path = flist_parent_dir.string() + '/' + v_file_name; - log("Verilog file %s\n", v_file_path.c_str()); - bool is_sv = (std::filesystem::path(v_file_path).extension() == ".sv"); + std::string verilog_file_path; + if (relative_to_file_list_path) { + verilog_file_path = file_list_parent_dir.string() + '/' + v_file_name; + } else { + verilog_file_path = std::filesystem::current_path().string() + '/' + v_file_name; + } + + bool is_sv = (std::filesystem::path(verilog_file_path).extension() == ".sv"); std::string command = "read_verilog"; if (is_sv) { command += " -sv"; } - command = command + ' ' + v_file_path; + command = command + ' ' + verilog_file_path; Pass::call(design, command); } - } - void parse_flist_rel_pwd(const std::string &flist_path, RTLIL::Design *design) { log("pwd %s\n", flist_path.c_str()); } + flist.close(); + } void execute(std::vector args, RTLIL::Design *design) override { @@ -731,20 +736,21 @@ struct VerilogFilelist : public Pass { for (argidx = 1; argidx < args.size(); argidx++) { std::string arg = args[argidx]; if (arg == "-F" && argidx + 1 < args.size()) { - std::string flist_path = args[++argidx]; - parse_flist_rel_filelist(flist_path, design); + std::string file_list_path = args[++argidx]; + parse_file_list(file_list_path, design, true); continue; } if (arg == "-f" && argidx + 1 < args.size()) { - std::string flist_path = args[++argidx]; - parse_flist_rel_pwd(flist_path, design); + std::string file_list_path = args[++argidx]; + parse_file_list(file_list_path, design, false); continue; } break; } - if (args.size() != argidx) + if (args.size() != argidx) { cmd_error(args, argidx, "Extra argument."); + } } } VerilogFilelist;