mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-21 21:33:40 +00:00
fmt: Extend string handling for SystemVerilog
This makes for a distinction between a string argument from a quoted literal, and a string argument from a variable or other expression.
This commit is contained in:
parent
71235f9b48
commit
0635df4ee5
3 changed files with 28 additions and 6 deletions
|
@ -337,7 +337,7 @@ void Fmt::parse_verilog(const std::vector<VerilogFmtArg> &args, bool sformat_lik
|
|||
}
|
||||
|
||||
case VerilogFmtArg::STRING: {
|
||||
if (arg == args.begin() || !sformat_like) {
|
||||
if ((arg == args.begin() || !sformat_like) && !arg->str.empty()) {
|
||||
const auto fmtarg = arg;
|
||||
const std::string &fmt = fmtarg->str;
|
||||
FmtPart part = {};
|
||||
|
@ -366,8 +366,19 @@ void Fmt::parse_verilog(const std::vector<VerilogFmtArg> &args, bool sformat_lik
|
|||
if (++arg == args.end()) {
|
||||
log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with fewer arguments than the format specifiers in argument %zu require.\n", task_name.c_str(), fmtarg - args.begin() + 1);
|
||||
}
|
||||
part.sig = arg->sig;
|
||||
part.signed_ = arg->signed_;
|
||||
switch (arg->type) {
|
||||
case VerilogFmtArg::STRING:
|
||||
part.sig = arg->str.empty() ? arg->sig : Const(arg->str);
|
||||
part.signed_ = false;
|
||||
break;
|
||||
case VerilogFmtArg::INTEGER:
|
||||
part.sig = arg->sig;
|
||||
part.signed_ = arg->signed_;
|
||||
break;
|
||||
default:
|
||||
// requires `%t`/`%T` which is enforced later on
|
||||
break;
|
||||
}
|
||||
|
||||
for (; i < fmt.size(); i++) {
|
||||
if (fmt[i] == '-') {
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue