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fmt: Extend string handling for SystemVerilog

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This makes for a distinction between a string argument from a quoted
literal, and a string argument from a variable or other expression.
This commit is contained in:
Martin Povišer 2024-02-08 15:03:38 +01:00
parent 71235f9b48
commit 0635df4ee5
3 changed files with 28 additions and 6 deletions
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2
frontends/ast/genrtlil.cc
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@ -771,8 +771,6 @@ struct AST_INTERNAL::ProcessGenerator
if (node->type == AST_CONSTANT && node->is_string) {
arg.type = VerilogFmtArg::STRING;
arg.str = node->bitsAsConst().decode_string();
// and in case this will be used as an argument...
arg.sig = node->bitsAsConst();
arg.signed_ = false;
} else if (node->type == AST_IDENTIFIER && node->str == "$time") {
arg.type = VerilogFmtArg::TIME;