From bbbce0d1c58f8bfb0a615f1ed53fa046552b5adf Mon Sep 17 00:00:00 2001 From: Claire Wolf Date: Mon, 27 Apr 2020 17:04:47 +0200 Subject: [PATCH 1/7] Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset, fixes #1990 Signed-off-by: Claire Wolf --- README.md | 3 +++ frontends/ast/ast.cc | 4 ++++ frontends/ast/ast.h | 2 ++ frontends/ast/genrtlil.cc | 4 ++++ frontends/ast/simplify.cc | 50 +++++++++++++++++++++++++++++++++------ kernel/constids.inc | 1 + 6 files changed, 57 insertions(+), 7 deletions(-) diff --git a/README.md b/README.md index 1e486c3ac..c17c0c3b1 100644 --- a/README.md +++ b/README.md @@ -281,6 +281,9 @@ Verilog Attributes and non-standard features temporary variable within an always block. This is mostly used internally by Yosys to synthesize Verilog functions and access arrays. +- The ``nowrshmsk`` attribute on a register prohibits the generation of + shift-and-mask type circuits for writing to bit slices of that register. + - The ``onehot`` attribute on wires mark them as one-hot state register. This is used for example for memory port sharing and set by the fsm_map pass. diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 6a9af3f57..8daae7dcb 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -110,6 +110,8 @@ std::string AST::type2str(AstNodeType type) X(AST_SHIFT_RIGHT) X(AST_SHIFT_SLEFT) X(AST_SHIFT_SRIGHT) + X(AST_SHIFTX) + X(AST_SHIFT) X(AST_LT) X(AST_LE) X(AST_EQ) @@ -628,6 +630,8 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const if (0) { case AST_SHIFT_RIGHT: txt = ">>"; } if (0) { case AST_SHIFT_SLEFT: txt = "<<<"; } if (0) { case AST_SHIFT_SRIGHT: txt = ">>>"; } + if (0) { case AST_SHIFTX: txt = "@shiftx@"; } + if (0) { case AST_SHIFT: txt = "@shift@"; } if (0) { case AST_LT: txt = "<"; } if (0) { case AST_LE: txt = "<="; } if (0) { case AST_EQ: txt = "=="; } diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 3f6329112..0baea7b63 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -91,6 +91,8 @@ namespace AST AST_SHIFT_RIGHT, AST_SHIFT_SLEFT, AST_SHIFT_SRIGHT, + AST_SHIFTX, + AST_SHIFT, AST_LT, AST_LE, AST_EQ, diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index d35335747..6a39bbc04 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -856,6 +856,8 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun case AST_SHIFT_RIGHT: case AST_SHIFT_SLEFT: case AST_SHIFT_SRIGHT: + case AST_SHIFTX: + case AST_SHIFT: case AST_POW: children[0]->detectSignWidthWorker(width_hint, sign_hint, found_real); break; @@ -1356,6 +1358,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (0) { case AST_SHIFT_RIGHT: type_name = ID($shr); } if (0) { case AST_SHIFT_SLEFT: type_name = ID($sshl); } if (0) { case AST_SHIFT_SRIGHT: type_name = ID($sshr); } + if (0) { case AST_SHIFTX: type_name = ID($shiftx); } + if (0) { case AST_SHIFT: type_name = ID($shift); } { if (width_hint < 0) detectSignWidth(width_hint, sign_hint); diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 837c14ad7..af347b8f1 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1786,7 +1786,18 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, result_width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1; } - if (0) + bool use_case_method = false; + + if (children[0]->id2ast->attributes.count(ID::nowrshmsk)) { + AstNode *node = children[0]->id2ast->attributes.at(ID::nowrshmsk); + while (node->simplify(true, false, false, stage, -1, false, false)) { } + if (node->type != AST_CONSTANT) + log_file_error(filename, location.first_line, "Non-constant value for `nowrshmsk' attribute on `%s'!\n", children[0]->id2ast->str.c_str()); + if (node->asAttrConst().as_bool()) + use_case_method = true; + } + + if (use_case_method) { // big case block @@ -1794,10 +1805,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, newNode = new AstNode(AST_CASE, shift_expr); for (int i = 0; i < source_width; i++) { int start_bit = children[0]->id2ast->range_right + i; + int end_bit = std::min(start_bit+result_width,source_width) - 1; AstNode *cond = new AstNode(AST_COND, mkconst_int(start_bit, true)); AstNode *lvalue = children[0]->clone(); lvalue->delete_children(); - int end_bit = std::min(start_bit+result_width,source_width) - 1; lvalue->children.push_back(new AstNode(AST_RANGE, mkconst_int(end_bit, true), mkconst_int(start_bit, true))); cond->children.push_back(new AstNode(AST_BLOCK, new AstNode(type, lvalue, children[1]->clone()))); @@ -1844,11 +1855,36 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, AstNode *shamt = shift_expr; - newNode->children.push_back(new AstNode(AST_ASSIGN_EQ, ref_mask->clone(), - new AstNode(AST_SHIFT_LEFT, mkconst_bits(std::vector(result_width, State::S1), false), shamt->clone()))); - newNode->children.push_back(new AstNode(AST_ASSIGN_EQ, ref_data->clone(), - new AstNode(AST_SHIFT_LEFT, new AstNode(AST_BIT_AND, mkconst_bits(std::vector(result_width, State::S1), false), children[1]->clone()), shamt))); - newNode->children.push_back(new AstNode(type, lvalue, new AstNode(AST_BIT_OR, new AstNode(AST_BIT_AND, old_data, new AstNode(AST_BIT_NOT, ref_mask)), ref_data))); + int start_bit = children[0]->id2ast->range_right; + bool use_shift = shamt->is_signed; + + if (start_bit != 0) { + shamt = new AstNode(AST_SUB, shamt, mkconst_int(start_bit, true)); + use_shift = true; + } + + AstNode *t; + + t = mkconst_bits(std::vector(result_width, State::S1), false); + if (use_shift) + t = new AstNode(AST_SHIFT, t, new AstNode(AST_NEG, shamt->clone())); + else + t = new AstNode(AST_SHIFT_LEFT, t, shamt->clone()); + t = new AstNode(AST_ASSIGN_EQ, ref_mask->clone(), t); + newNode->children.push_back(t); + + t = new AstNode(AST_BIT_AND, mkconst_bits(std::vector(result_width, State::S1), false), children[1]->clone()); + if (use_shift) + t = new AstNode(AST_SHIFT, t, new AstNode(AST_NEG, shamt)); + else + t = new AstNode(AST_SHIFT_LEFT, t, shamt); + t = new AstNode(AST_ASSIGN_EQ, ref_data->clone(), t); + newNode->children.push_back(t); + + t = new AstNode(AST_BIT_AND, old_data, new AstNode(AST_BIT_NOT, ref_mask)); + t = new AstNode(AST_BIT_OR, t, ref_data); + t = new AstNode(type, lvalue, t); + newNode->children.push_back(t); } goto apply_newNode; diff --git a/kernel/constids.inc b/kernel/constids.inc index 27b652e24..4f8e86969 100644 --- a/kernel/constids.inc +++ b/kernel/constids.inc @@ -123,6 +123,7 @@ X(nomem2init) X(nomem2reg) X(nomeminit) X(nosync) +X(nowrshmsk) X(O) X(OFFSET) X(onehot) From 589ed2d97032829568e73a5858772e39088aeeeb Mon Sep 17 00:00:00 2001 From: Claire Wolf Date: Wed, 29 Apr 2020 14:28:04 +0200 Subject: [PATCH 2/7] Add AST_SELFSZ and improve handling of bit slices Signed-off-by: Claire Wolf --- frontends/ast/ast.cc | 2 ++ frontends/ast/ast.h | 1 + frontends/ast/genrtlil.cc | 8 +++++++- frontends/ast/simplify.cc | 14 ++++++++++---- frontends/verilog/verilog_parser.y | 4 ++-- 5 files changed, 22 insertions(+), 7 deletions(-) diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 8daae7dcb..689fa9fb4 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -94,6 +94,7 @@ std::string AST::type2str(AstNodeType type) X(AST_TO_BITS) X(AST_TO_SIGNED) X(AST_TO_UNSIGNED) + X(AST_SELFSZ) X(AST_CONCAT) X(AST_REPLICATE) X(AST_BIT_NOT) @@ -617,6 +618,7 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const if (0) { case AST_POS: txt = "+"; } if (0) { case AST_NEG: txt = "-"; } if (0) { case AST_LOGIC_NOT: txt = "!"; } + if (0) { case AST_SELFSZ: txt = "@selfsz@"; } fprintf(f, "%s(", txt.c_str()); children[0]->dumpVlog(f, ""); fprintf(f, ")"); diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 0baea7b63..8932108e3 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -75,6 +75,7 @@ namespace AST AST_TO_BITS, AST_TO_SIGNED, AST_TO_UNSIGNED, + AST_SELFSZ, AST_CONCAT, AST_REPLICATE, AST_BIT_NOT, diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 6a39bbc04..37cbb8a83 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -809,6 +809,11 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun sign_hint = false; break; + case AST_SELFSZ: + sub_width_hint = 0; + children.at(0)->detectSignWidthWorker(sub_width_hint, sign_hint); + break; + case AST_CONCAT: for (auto child : children) { sub_width_hint = 0; @@ -1267,7 +1272,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // just pass thru the signal. the parent will evaluate the is_signed property and interpret the SigSpec accordingly case AST_TO_SIGNED: - case AST_TO_UNSIGNED: { + case AST_TO_UNSIGNED: + case AST_SELFSZ: { RTLIL::SigSpec sig = children[0]->genRTLIL(); if (sig.size() < width_hint) sig.extend_u0(width_hint, sign_hint); diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index af347b8f1..af5e14217 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -608,6 +608,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, case AST_TO_BITS: case AST_TO_SIGNED: case AST_TO_UNSIGNED: + case AST_SELFSZ: case AST_CONCAT: case AST_REPLICATE: case AST_REDUCE_AND: @@ -1855,8 +1856,12 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, AstNode *shamt = shift_expr; + int shamt_width_hint = 0; + bool shamt_sign_hint = true; + shamt->detectSignWidth(shamt_width_hint, shamt_sign_hint); + int start_bit = children[0]->id2ast->range_right; - bool use_shift = shamt->is_signed; + bool use_shift = shamt_sign_hint; if (start_bit != 0) { shamt = new AstNode(AST_SUB, shamt, mkconst_int(start_bit, true)); @@ -3060,6 +3065,7 @@ replace_fcall_later:; } } break; + if (0) { case AST_SELFSZ: const_func = RTLIL::const_pos; } if (0) { case AST_POS: const_func = RTLIL::const_pos; } if (0) { case AST_NEG: const_func = RTLIL::const_neg; } if (children[0]->type == AST_CONSTANT) { @@ -3068,10 +3074,10 @@ replace_fcall_later:; } else if (children[0]->isConst()) { newNode = new AstNode(AST_REALVALUE); - if (type == AST_POS) - newNode->realvalue = +children[0]->asReal(sign_hint); - else + if (type == AST_NEG) newNode->realvalue = -children[0]->asReal(sign_hint); + else + newNode->realvalue = +children[0]->asReal(sign_hint); } break; case AST_TERNARY: diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 4a5aba79e..903c8e77f 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -645,13 +645,13 @@ non_opt_range: } | '[' expr TOK_POS_INDEXED expr ']' { $$ = new AstNode(AST_RANGE); - AstNode *expr = new AstNode(AST_CONCAT, $2); + AstNode *expr = new AstNode(AST_SELFSZ, $2); $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, expr->clone(), $4), AstNode::mkconst_int(1, true))); $$->children.push_back(new AstNode(AST_ADD, expr, AstNode::mkconst_int(0, true))); } | '[' expr TOK_NEG_INDEXED expr ']' { $$ = new AstNode(AST_RANGE); - AstNode *expr = new AstNode(AST_CONCAT, $2); + AstNode *expr = new AstNode(AST_SELFSZ, $2); $$->children.push_back(new AstNode(AST_ADD, expr, AstNode::mkconst_int(0, true))); $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, expr->clone(), AstNode::mkconst_int(1, true)), $4)); } | From 749c2ff84a618cdb1d0c38fefde9445ece42e6fb Mon Sep 17 00:00:00 2001 From: Claire Wolf Date: Wed, 29 Apr 2020 14:28:54 +0200 Subject: [PATCH 3/7] Add tests based on the test case from #1990 Signed-off-by: Claire Wolf --- tests/simple/partsel.v | 46 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/tests/simple/partsel.v b/tests/simple/partsel.v index 83493fcb0..dd66ded55 100644 --- a/tests/simple/partsel.v +++ b/tests/simple/partsel.v @@ -64,3 +64,49 @@ endmodule module partsel_test003(input [2:0] a, b, input [31:0] din, output [3:0] dout); assign dout = din[a*b +: 2]; endmodule + +module partsel_test004 ( + input [31:0] din, + input signed [4:0] n, + output reg [31:0] dout +); + always @(*) begin + dout = 0; + dout[n+1 +: 2] = din[n +: 2]; + end +endmodule + + +module partsel_test005 ( + input [31:0] din, + input signed [4:0] n, + output reg [31:0] dout +); + always @(*) begin + dout = 0; + dout[n+1] = din[n]; + end +endmodule + +module partsel_test006 ( + input [31:0] din, + input signed [4:0] n, + output reg [31:-32] dout +); + always @(*) begin + dout = 0; + dout[n+1 +: 2] = din[n +: 2]; + end +endmodule + + +module partsel_test007 ( + input [31:0] din, + input signed [4:0] n, + output reg [31:-32] dout +); + always @(*) begin + dout = 0; + dout[n+1] = din[n]; + end +endmodule From 88185f8959dc53fd60605747cc93a6129fc1bab3 Mon Sep 17 00:00:00 2001 From: Claire Wolf Date: Fri, 1 May 2020 17:25:33 +0200 Subject: [PATCH 4/7] Fix handling of signed indices in bit slices Signed-off-by: Claire Wolf --- frontends/ast/genrtlil.cc | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 37cbb8a83..85d8e106b 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1212,13 +1212,18 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) AstNode *fake_ast = new AstNode(AST_NONE, clone(), children[0]->children.size() >= 2 ? children[0]->children[1]->clone() : children[0]->children[0]->clone()); fake_ast->children[0]->delete_children(); - RTLIL::SigSpec shift_val = fake_ast->children[1]->genRTLIL(); + + int fake_ast_width = 0; + bool fake_ast_sign = true; + fake_ast->children[1]->detectSignWidth(fake_ast_width, fake_ast_sign); + RTLIL::SigSpec shift_val = fake_ast->children[1]->genRTLIL(fake_ast_width, fake_ast_sign); + if (id2ast->range_right != 0) { - shift_val = current_module->Sub(NEW_ID, shift_val, id2ast->range_right, fake_ast->children[1]->is_signed); + shift_val = current_module->Sub(NEW_ID, shift_val, id2ast->range_right, fake_ast_sign); fake_ast->children[1]->is_signed = true; } if (id2ast->range_swapped) { - shift_val = current_module->Sub(NEW_ID, RTLIL::SigSpec(source_width - width), shift_val, fake_ast->children[1]->is_signed); + shift_val = current_module->Sub(NEW_ID, RTLIL::SigSpec(source_width - width), shift_val, fake_ast_sign); fake_ast->children[1]->is_signed = true; } if (GetSize(shift_val) >= 32) From f38d76efbfa456533837d614822d2b89302386f9 Mon Sep 17 00:00:00 2001 From: Claire Wolf Date: Fri, 1 May 2020 17:26:07 +0200 Subject: [PATCH 5/7] Bugfix in partsel.v signed indices test cases Signed-off-by: Claire Wolf --- tests/simple/partsel.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/simple/partsel.v b/tests/simple/partsel.v index dd66ded55..5e9730d6b 100644 --- a/tests/simple/partsel.v +++ b/tests/simple/partsel.v @@ -89,7 +89,7 @@ module partsel_test005 ( endmodule module partsel_test006 ( - input [31:0] din, + input [31:-32] din, input signed [4:0] n, output reg [31:-32] dout ); @@ -101,7 +101,7 @@ endmodule module partsel_test007 ( - input [31:0] din, + input [31:-32] din, input signed [4:0] n, output reg [31:-32] dout ); From c3e5a070eac753cfd54058f7e186bad0742301ed Mon Sep 17 00:00:00 2001 From: Claire Wolf Date: Fri, 1 May 2020 17:26:34 +0200 Subject: [PATCH 6/7] Add plusargs for output files in test_autotb output Signed-off-by: Claire Wolf --- passes/tests/test_autotb.cc | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc index 42e8a61ea..19f21493d 100644 --- a/passes/tests/test_autotb.cc +++ b/passes/tests/test_autotb.cc @@ -81,6 +81,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s f << stringf("integer i;\n"); f << stringf("integer file;\n\n"); + f << stringf("reg [1023:0] filename;\n\n"); f << stringf("reg [31:0] xorshift128_x = 123456789;\n"); f << stringf("reg [31:0] xorshift128_y = 362436069;\n"); @@ -305,9 +306,15 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s } f << stringf("initial begin\n"); - f << stringf("\t// $dumpfile(\"testbench.vcd\");\n"); - f << stringf("\t// $dumpvars(0, testbench);\n"); - f << stringf("\tfile = $fopen(`outfile);\n"); + f << stringf("\tif ($value$plusargs(\"VCD=%%s\", filename)) begin\n"); + f << stringf("\t\t$dumpfile(filename);\n"); + f << stringf("\t\t$dumpvars(0, testbench);\n"); + f << stringf("\tend\n"); + f << stringf("\tif ($value$plusargs(\"OUT=%%s\", filename)) begin\n"); + f << stringf("\t\tfile = $fopen(filename);\n"); + f << stringf("\tend else begin\n"); + f << stringf("\t\tfile = $fopen(`outfile);\n"); + f << stringf("\tend\n"); for (auto module : design->modules()) if (!module->get_bool_attribute(ID::gentb_skip)) f << stringf("\t%s;\n", idy(module->name.str(), "test").c_str()); From 885deb4e88e847e1314b8a67087f72c3809a6995 Mon Sep 17 00:00:00 2001 From: Claire Wolf Date: Sat, 2 May 2020 21:34:24 +0200 Subject: [PATCH 7/7] Fix the other "opt_expr -fine" bug introduced in 213a89558 Signed-off-by: Claire Wolf --- passes/opt/opt_expr.cc | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 3f664c8d1..0f5bff680 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -728,6 +728,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons RTLIL::SigSpec sig_x = cell->getPort(ID::X); RTLIL::SigSpec sig_y = cell->getPort(ID::Y); RTLIL::SigSpec sig_co = cell->getPort(ID::CO); + bool is_signed = cell->getParam(ID::A_SIGNED).as_bool(); if (sig_bi != State::S0 && sig_bi != State::S1) goto skip_fine_alu; @@ -737,16 +738,20 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons bool bi = sig_bi == State::S1; bool ci = sig_ci == State::S1; + int minsz = GetSize(sig_y); + minsz = std::min(minsz, GetSize(sig_a)); + minsz = std::min(minsz, GetSize(sig_b)); + int i; - for (i = 0; i < GetSize(sig_y); i++) { - RTLIL::SigBit b = sig_b.at(i, State::Sx); - RTLIL::SigBit a = sig_a.at(i, State::Sx); - if (b == ((bi ^ ci) ? State::S1 : State::S0) && a != State::Sx) { + for (i = 0; i < minsz; i++) { + RTLIL::SigBit b = sig_b[i]; + RTLIL::SigBit a = sig_a[i]; + if (b == ((bi ^ ci) ? State::S1 : State::S0)) { module->connect(sig_y[i], a); module->connect(sig_x[i], ci ? module->Not(NEW_ID, a).as_bit() : a); module->connect(sig_co[i], ci ? State::S1 : State::S0); } - else if (a == (ci ? State::S1 : State::S0) && b != State::Sx) { + else if (a == (ci ? State::S1 : State::S0)) { module->connect(sig_y[i], bi ? module->Not(NEW_ID, b).as_bit() : b); module->connect(sig_x[i], (bi ^ ci) ? module->Not(NEW_ID, b).as_bit() : b); module->connect(sig_co[i], ci ? State::S1 : State::S0); @@ -756,8 +761,15 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } if (i > 0) { cover("opt.opt_expr.fine.$alu"); - cell->setPort(ID::A, sig_a.extract_end(i)); - cell->setPort(ID::B, sig_b.extract_end(i)); + log_debug("Stripping %d LSB bits of %s cell %s in module %s.\n", i, log_id(cell->type), log_id(cell), log_id(module)); + SigSpec new_a = sig_a.extract_end(i); + SigSpec new_b = sig_b.extract_end(i); + if (new_a.empty() && is_signed) + new_a = sig_a[i-1]; + if (new_b.empty() && is_signed) + new_b = sig_b[i-1]; + cell->setPort(ID::A, new_a); + cell->setPort(ID::B, new_b); cell->setPort(ID::X, sig_x.extract_end(i)); cell->setPort(ID::Y, sig_y.extract_end(i)); cell->setPort(ID::CO, sig_co.extract_end(i));