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https://github.com/YosysHQ/yosys
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Fix formatting for synth_intel.cc
This is realized through the recently added .clang-format file. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
This commit is contained in:
Ben Widawsky
parent
02e7d931a7
commit
05d8cc4567
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@ -17,254 +17,243 @@
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*
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*
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*/
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/celltypes.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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#include "kernel/log.h"
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#include "kernel/register.h"
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#include "kernel/rtlil.h"
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USING_YOSYS_NAMESPACE
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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PRIVATE_NAMESPACE_BEGIN
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struct SynthIntelPass : public ScriptPass {
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struct SynthIntelPass : public ScriptPass {
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SynthIntelPass() : ScriptPass("synth_intel", "synthesis for Intel (Altera) FPGAs.") { }
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SynthIntelPass() : ScriptPass("synth_intel", "synthesis for Intel (Altera) FPGAs.") {}
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void help() YS_OVERRIDE
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void help() YS_OVERRIDE
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{
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log("\n");
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log(" synth_intel [options]\n");
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log(" synth_intel [options]\n");
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log("\n");
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log("\n");
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log("This command runs synthesis for Intel FPGAs.\n");
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log("This command runs synthesis for Intel FPGAs.\n");
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log("\n");
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log("\n");
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log(" -family < max10 | a10gx | cyclone10 | cyclonev | cycloneiv | cycloneive>\n");
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log(" -family < max10 | a10gx | cyclone10 | cyclonev | cycloneiv | cycloneive>\n");
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log(" generate the synthesis netlist for the specified family.\n");
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log(" generate the synthesis netlist for the specified family.\n");
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log(" MAX10 is the default target if not family argument specified.\n");
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log(" MAX10 is the default target if not family argument specified.\n");
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log(" For Cyclone GX devices, use cycloneiv argument; For Cyclone E, use cycloneive.\n");
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log(" For Cyclone GX devices, use cycloneiv argument; For Cyclone E, use cycloneive.\n");
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log(" Cyclone V and Arria 10 GX devices are experimental, use it with a10gx argument.\n");
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log(" Cyclone V and Arria 10 GX devices are experimental, use it with a10gx argument.\n");
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log("\n");
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log("\n");
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log(" -top <module>\n");
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log(" -top <module>\n");
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log(" use the specified module as top module (default='top')\n");
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log(" use the specified module as top module (default='top')\n");
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log("\n");
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log("\n");
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log(" -vqm <file>\n");
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log(" -vqm <file>\n");
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log(" write the design to the specified Verilog Quartus Mapping File. Writing of an\n");
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log(" write the design to the specified Verilog Quartus Mapping File. Writing of an\n");
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log(" output file is omitted if this parameter is not specified.\n");
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log(" output file is omitted if this parameter is not specified.\n");
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log("\n");
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log("\n");
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log(" -vpr <file>\n");
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log(" -vpr <file>\n");
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log(" write BLIF files for VPR flow experiments. The synthesized BLIF output file is not\n");
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log(" write BLIF files for VPR flow experiments. The synthesized BLIF output file is not\n");
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log(" compatible with the Quartus flow. Writing of an\n");
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log(" compatible with the Quartus flow. Writing of an\n");
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log(" output file is omitted if this parameter is not specified.\n");
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log(" output file is omitted if this parameter is not specified.\n");
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log("\n");
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log("\n");
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log(" -run <from_label>:<to_label>\n");
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log(" -run <from_label>:<to_label>\n");
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log(" only run the commands between the labels (see below). an empty\n");
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log(" only run the commands between the labels (see below). an empty\n");
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log(" from label is synonymous to 'begin', and empty to label is\n");
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log(" from label is synonymous to 'begin', and empty to label is\n");
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log(" synonymous to the end of the command list.\n");
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log(" synonymous to the end of the command list.\n");
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log("\n");
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log("\n");
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log(" -noiopads\n");
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log(" -noiopads\n");
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log(" do not use altsyncram cells in output netlist\n");
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log(" do not use altsyncram cells in output netlist\n");
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log("\n");
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log("\n");
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log(" -nobram\n");
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log(" -nobram\n");
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log(" do not use altsyncram cells in output netlist\n");
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log(" do not use altsyncram cells in output netlist\n");
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log("\n");
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log("\n");
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log(" -noflatten\n");
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log(" -noflatten\n");
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log(" do not flatten design before synthesis\n");
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log(" do not flatten design before synthesis\n");
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log("\n");
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log("\n");
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log(" -retime\n");
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log(" -retime\n");
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log(" run 'abc' with -dff option\n");
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log(" run 'abc' with -dff option\n");
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log("\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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log("The following commands are executed by this synthesis command:\n");
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help_script();
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help_script();
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log("\n");
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log("\n");
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}
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}
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string top_opt, family_opt, vout_file, blif_file;
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string top_opt, family_opt, vout_file, blif_file;
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bool retime, flatten, nobram, noiopads;
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bool retime, flatten, nobram, noiopads;
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void clear_flags() YS_OVERRIDE
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void clear_flags() YS_OVERRIDE
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{
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{
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top_opt = "-auto-top";
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top_opt = "-auto-top";
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family_opt = "max10";
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family_opt = "max10";
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vout_file = "";
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vout_file = "";
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blif_file = "";
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blif_file = "";
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retime = false;
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retime = false;
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flatten = true;
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flatten = true;
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nobram = false;
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nobram = false;
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noiopads = false;
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noiopads = false;
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}
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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{
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string run_from, run_to;
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string run_from, run_to;
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clear_flags();
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clear_flags();
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size_t argidx;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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for (argidx = 1; argidx < args.size(); argidx++) {
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{
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if (args[argidx] == "-family" && argidx + 1 < args.size()) {
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if (args[argidx] == "-family" && argidx+1 < args.size()) {
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family_opt = args[++argidx];
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family_opt = args[++argidx];
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continue;
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continue;
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}
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}
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if (args[argidx] == "-top" && argidx + 1 < args.size()) {
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if (args[argidx] == "-top" && argidx+1 < args.size()) {
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top_opt = "-top " + args[++argidx];
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top_opt = "-top " + args[++argidx];
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continue;
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continue;
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}
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}
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if (args[argidx] == "-vqm" && argidx + 1 < args.size()) {
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if (args[argidx] == "-vqm" && argidx+1 < args.size()) {
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vout_file = args[++argidx];
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vout_file = args[++argidx];
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continue;
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continue;
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}
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}
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if (args[argidx] == "-vpr" && argidx + 1 < args.size()) {
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if (args[argidx] == "-vpr" && argidx+1 < args.size()) {
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blif_file = args[++argidx];
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blif_file = args[++argidx];
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continue;
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continue;
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}
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}
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if (args[argidx] == "-run" && argidx + 1 < args.size()) {
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if (args[argidx] == "-run" && argidx+1 < args.size()) {
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size_t pos = args[argidx + 1].find(':');
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size_t pos = args[argidx+1].find(':');
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if (pos == std::string::npos)
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if (pos == std::string::npos)
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break;
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break;
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run_from = args[++argidx].substr(0, pos);
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run_from = args[++argidx].substr(0, pos);
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run_to = args[argidx].substr(pos + 1);
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run_to = args[argidx].substr(pos+1);
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continue;
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continue;
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}
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}
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if (args[argidx] == "-noiopads") {
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if (args[argidx] == "-noiopads") {
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noiopads = true;
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noiopads = true;
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continue;
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continue;
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}
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}
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if (args[argidx] == "-nobram") {
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if (args[argidx] == "-nobram") {
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nobram = true;
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nobram = true;
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continue;
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continue;
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}
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}
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if (args[argidx] == "-noflatten") {
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if (args[argidx] == "-noflatten") {
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flatten = false;
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flatten = false;
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continue;
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continue;
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}
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}
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if (args[argidx] == "-retime") {
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if (args[argidx] == "-retime") {
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retime = true;
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retime = true;
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continue;
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continue;
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}
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}
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break;
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break;
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}
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}
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extra_args(args, argidx, design);
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extra_args(args, argidx, design);
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if (!design->full_selection())
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if (!design->full_selection())
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log_cmd_error("This command only operates on fully selected designs!\n");
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log_cmd_error("This command only operates on fully selected designs!\n");
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if (family_opt != "max10" && family_opt !="a10gx" && family_opt != "cyclonev" && family_opt !="cycloneiv" && family_opt !="cycloneive" && family_opt != "cyclone10")
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if (family_opt != "max10" && family_opt != "a10gx" && family_opt != "cyclonev" && family_opt != "cycloneiv" &&
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log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str());
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family_opt != "cycloneive" && family_opt != "cyclone10")
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log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str());
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log_header(design, "Executing SYNTH_INTEL pass.\n");
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log_header(design, "Executing SYNTH_INTEL pass.\n");
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log_push();
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log_push();
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run_script(design, run_from, run_to);
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run_script(design, run_from, run_to);
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log_pop();
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log_pop();
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}
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}
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void script() YS_OVERRIDE
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void script() YS_OVERRIDE
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{
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{
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if (check_label("begin"))
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if (check_label("begin")) {
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{
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if (check_label("family") && family_opt == "max10")
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if(check_label("family") && family_opt=="max10")
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run("read_verilog -sv -lib +/intel/max10/cells_sim.v");
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run("read_verilog -sv -lib +/intel/max10/cells_sim.v");
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else if (check_label("family") && family_opt == "a10gx")
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else if(check_label("family") && family_opt=="a10gx")
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run("read_verilog -sv -lib +/intel/a10gx/cells_sim.v");
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run("read_verilog -sv -lib +/intel/a10gx/cells_sim.v");
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else if (check_label("family") && family_opt == "cyclonev")
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else if(check_label("family") && family_opt=="cyclonev")
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run("read_verilog -sv -lib +/intel/cyclonev/cells_sim.v");
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run("read_verilog -sv -lib +/intel/cyclonev/cells_sim.v");
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else if (check_label("family") && family_opt == "cyclone10")
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else if(check_label("family") && family_opt=="cyclone10")
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run("read_verilog -sv -lib +/intel/cyclone10/cells_sim.v");
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run("read_verilog -sv -lib +/intel/cyclone10/cells_sim.v");
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else if (check_label("family") && family_opt == "cycloneiv")
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else if(check_label("family") && family_opt=="cycloneiv")
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run("read_verilog -sv -lib +/intel/cycloneiv/cells_sim.v");
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run("read_verilog -sv -lib +/intel/cycloneiv/cells_sim.v");
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else
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else
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run("read_verilog -sv -lib +/intel/cycloneive/cells_sim.v");
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run("read_verilog -sv -lib +/intel/cycloneive/cells_sim.v");
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// Misc and common cells
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// Misc and common cells
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run("read_verilog -sv -lib +/intel/common/m9k_bb.v");
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run("read_verilog -sv -lib +/intel/common/m9k_bb.v");
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run("read_verilog -sv -lib +/intel/common/altpll_bb.v");
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run("read_verilog -sv -lib +/intel/common/altpll_bb.v");
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run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
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run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
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}
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}
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if (flatten && check_label("flatten", "(unless -noflatten)"))
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if (flatten && check_label("flatten", "(unless -noflatten)")) {
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{
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run("proc");
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run("proc");
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run("flatten");
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run("flatten");
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run("tribuf -logic");
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run("tribuf -logic");
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run("deminout");
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run("deminout");
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}
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}
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if (check_label("coarse"))
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if (check_label("coarse")) {
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{
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run("synth -run coarse");
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run("synth -run coarse");
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}
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}
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if (!nobram && check_label("bram", "(skip if -nobram)"))
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if (!nobram && check_label("bram", "(skip if -nobram)")) {
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{
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run("memory_bram -rules +/intel/common/brams.txt");
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run("memory_bram -rules +/intel/common/brams.txt");
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run("techmap -map +/intel/common/brams_map.v");
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run("techmap -map +/intel/common/brams_map.v");
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}
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}
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if (check_label("fine"))
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if (check_label("fine")) {
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{
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run("opt -fast -mux_undef -undriven -fine -full");
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run("opt -fast -mux_undef -undriven -fine -full");
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run("memory_map");
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run("memory_map");
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run("opt -undriven -fine");
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run("opt -undriven -fine");
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run("dffsr2dff");
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run("dffsr2dff");
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run("dff2dffe -direct-match $_DFF_*");
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run("dff2dffe -direct-match $_DFF_*");
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run("opt -fine");
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run("opt -fine");
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run("techmap -map +/techmap.v");
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run("techmap -map +/techmap.v");
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run("opt -full");
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run("opt -full");
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run("clean -purge");
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run("clean -purge");
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run("setundef -undriven -zero");
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run("setundef -undriven -zero");
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if (retime || help_mode)
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if (retime || help_mode)
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run("abc -markgroups -dff", "(only if -retime)");
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run("abc -markgroups -dff", "(only if -retime)");
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}
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}
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if (check_label("map_luts"))
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if (check_label("map_luts")) {
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{
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if (family_opt == "a10gx" || family_opt == "cyclonev")
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if(family_opt=="a10gx" || family_opt=="cyclonev")
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run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
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run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
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else
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else
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run("abc -lut 4" + string(retime ? " -dff" : ""));
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run("abc -lut 4" + string(retime ? " -dff" : ""));
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run("clean");
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run("clean");
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}
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}
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if (check_label("map_cells"))
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if (check_label("map_cells")) {
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{
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if (!noiopads)
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if (!noiopads)
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run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(unless -noiopads)");
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run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(unless -noiopads)");
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if (family_opt == "max10")
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if(family_opt=="max10")
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run("techmap -map +/intel/max10/cells_map.v");
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run("techmap -map +/intel/max10/cells_map.v");
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else if (family_opt == "a10gx")
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else if(family_opt=="a10gx")
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run("techmap -map +/intel/a10gx/cells_map.v");
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run("techmap -map +/intel/a10gx/cells_map.v");
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else if (family_opt == "cyclonev")
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else if(family_opt=="cyclonev")
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run("techmap -map +/intel/cyclonev/cells_map.v");
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run("techmap -map +/intel/cyclonev/cells_map.v");
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else if (family_opt == "cyclone10")
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else if(family_opt=="cyclone10")
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run("techmap -map +/intel/cyclone10/cells_map.v");
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run("techmap -map +/intel/cyclone10/cells_map.v");
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else if (family_opt == "cycloneiv")
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else if(family_opt=="cycloneiv")
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run("techmap -map +/intel/cycloneiv/cells_map.v");
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run("techmap -map +/intel/cycloneiv/cells_map.v");
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else
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else
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run("techmap -map +/intel/cycloneive/cells_map.v");
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run("techmap -map +/intel/cycloneive/cells_map.v");
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run("dffinit -highlow -ff dffeas q power_up");
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run("dffinit -highlow -ff dffeas q power_up");
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run("clean -purge");
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run("clean -purge");
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}
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}
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if (check_label("check"))
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if (check_label("check")) {
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{
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run("hierarchy -check");
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run("hierarchy -check");
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run("stat");
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run("stat");
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run("check -noinit");
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run("check -noinit");
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}
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}
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if (check_label("vqm"))
|
if (check_label("vqm")) {
|
||||||
{
|
if (!vout_file.empty() || help_mode)
|
||||||
if (!vout_file.empty() || help_mode)
|
run(stringf("write_verilog -attr2comment -defparam -nohex -decimal -renameprefix syn_ %s",
|
||||||
run(stringf("write_verilog -attr2comment -defparam -nohex -decimal -renameprefix syn_ %s",
|
help_mode ? "<file-name>" : vout_file.c_str()));
|
||||||
help_mode ? "<file-name>" : vout_file.c_str()));
|
}
|
||||||
}
|
|
||||||
|
|
||||||
if (check_label("vpr"))
|
if (check_label("vpr")) {
|
||||||
{
|
if (!blif_file.empty() || help_mode) {
|
||||||
if (!blif_file.empty() || help_mode)
|
run(stringf("opt_clean -purge"));
|
||||||
{
|
run(stringf("write_blif %s", help_mode ? "<file-name>" : blif_file.c_str()));
|
||||||
run(stringf("opt_clean -purge"));
|
}
|
||||||
run(stringf("write_blif %s", help_mode ? "<file-name>" : blif_file.c_str()));
|
}
|
||||||
}
|
}
|
||||||
}
|
|
||||||
}
|
|
||||||
} SynthIntelPass;
|
} SynthIntelPass;
|
||||||
|
|
||||||
PRIVATE_NAMESPACE_END
|
PRIVATE_NAMESPACE_END
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue