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Fix formatting for synth_intel.cc

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This is realized through the recently added .clang-format file.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
This commit is contained in:
Ben Widawsky 2019-05-04 10:36:06 -07:00
parent 02e7d931a7
commit 05d8cc4567
1 changed files with 211 additions and 222 deletions
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81
techlibs/intel/synth_intel.cc
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@ -17,16 +17,16 @@
* *
*/ */
#include "kernel/register.h"
#include "kernel/celltypes.h" #include "kernel/celltypes.h"
#include "kernel/rtlil.h"
#include "kernel/log.h" #include "kernel/log.h"
#include "kernel/register.h"
#include "kernel/rtlil.h"
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
struct SynthIntelPass : public ScriptPass { struct SynthIntelPass : public ScriptPass {
SynthIntelPass() : ScriptPass("synth_intel", "synthesis for Intel (Altera) FPGAs.") { } SynthIntelPass() : ScriptPass("synth_intel", "synthesis for Intel (Altera) FPGAs.") {}
void help() YS_OVERRIDE void help() YS_OVERRIDE
{ {
@ -97,30 +97,29 @@ struct SynthIntelPass : public ScriptPass {
clear_flags(); clear_flags();
size_t argidx; size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) for (argidx = 1; argidx < args.size(); argidx++) {
{ if (args[argidx] == "-family" && argidx + 1 < args.size()) {
if (args[argidx] == "-family" && argidx+1 < args.size()) {
family_opt = args[++argidx]; family_opt = args[++argidx];
continue; continue;
} }
if (args[argidx] == "-top" && argidx+1 < args.size()) { if (args[argidx] == "-top" && argidx + 1 < args.size()) {
top_opt = "-top " + args[++argidx]; top_opt = "-top " + args[++argidx];
continue; continue;
} }
if (args[argidx] == "-vqm" && argidx+1 < args.size()) { if (args[argidx] == "-vqm" && argidx + 1 < args.size()) {
vout_file = args[++argidx]; vout_file = args[++argidx];
continue; continue;
} }
if (args[argidx] == "-vpr" && argidx+1 < args.size()) { if (args[argidx] == "-vpr" && argidx + 1 < args.size()) {
blif_file = args[++argidx]; blif_file = args[++argidx];
continue; continue;
} }
if (args[argidx] == "-run" && argidx+1 < args.size()) { if (args[argidx] == "-run" && argidx + 1 < args.size()) {
size_t pos = args[argidx+1].find(':'); size_t pos = args[argidx + 1].find(':');
if (pos == std::string::npos) if (pos == std::string::npos)
break; break;
run_from = args[++argidx].substr(0, pos); run_from = args[++argidx].substr(0, pos);
run_to = args[argidx].substr(pos+1); run_to = args[argidx].substr(pos + 1);
continue; continue;
} }
if (args[argidx] == "-noiopads") { if (args[argidx] == "-noiopads") {
@ -145,7 +144,8 @@ struct SynthIntelPass : public ScriptPass {
if (!design->full_selection()) if (!design->full_selection())
log_cmd_error("This command only operates on fully selected designs!\n"); log_cmd_error("This command only operates on fully selected designs!\n");
if (family_opt != "max10" && family_opt !="a10gx" && family_opt != "cyclonev" && family_opt !="cycloneiv" && family_opt !="cycloneive" && family_opt != "cyclone10") if (family_opt != "max10" && family_opt != "a10gx" && family_opt != "cyclonev" && family_opt != "cycloneiv" &&
family_opt != "cycloneive" && family_opt != "cyclone10")
log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str()); log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str());
log_header(design, "Executing SYNTH_INTEL pass.\n"); log_header(design, "Executing SYNTH_INTEL pass.\n");
@ -158,17 +158,16 @@ struct SynthIntelPass : public ScriptPass {
void script() YS_OVERRIDE void script() YS_OVERRIDE
{ {
if (check_label("begin")) if (check_label("begin")) {
{ if (check_label("family") && family_opt == "max10")
if(check_label("family") && family_opt=="max10")
run("read_verilog -sv -lib +/intel/max10/cells_sim.v"); run("read_verilog -sv -lib +/intel/max10/cells_sim.v");
else if(check_label("family") && family_opt=="a10gx") else if (check_label("family") && family_opt == "a10gx")
run("read_verilog -sv -lib +/intel/a10gx/cells_sim.v"); run("read_verilog -sv -lib +/intel/a10gx/cells_sim.v");
else if(check_label("family") && family_opt=="cyclonev") else if (check_label("family") && family_opt == "cyclonev")
run("read_verilog -sv -lib +/intel/cyclonev/cells_sim.v"); run("read_verilog -sv -lib +/intel/cyclonev/cells_sim.v");
else if(check_label("family") && family_opt=="cyclone10") else if (check_label("family") && family_opt == "cyclone10")
run("read_verilog -sv -lib +/intel/cyclone10/cells_sim.v"); run("read_verilog -sv -lib +/intel/cyclone10/cells_sim.v");
else if(check_label("family") && family_opt=="cycloneiv") else if (check_label("family") && family_opt == "cycloneiv")
run("read_verilog -sv -lib +/intel/cycloneiv/cells_sim.v"); run("read_verilog -sv -lib +/intel/cycloneiv/cells_sim.v");
else else
run("read_verilog -sv -lib +/intel/cycloneive/cells_sim.v"); run("read_verilog -sv -lib +/intel/cycloneive/cells_sim.v");
@ -178,27 +177,23 @@ struct SynthIntelPass : public ScriptPass {
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str())); run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
} }
if (flatten && check_label("flatten", "(unless -noflatten)")) if (flatten && check_label("flatten", "(unless -noflatten)")) {
{
run("proc"); run("proc");
run("flatten"); run("flatten");
run("tribuf -logic"); run("tribuf -logic");
run("deminout"); run("deminout");
} }
if (check_label("coarse")) if (check_label("coarse")) {
{
run("synth -run coarse"); run("synth -run coarse");
} }
if (!nobram && check_label("bram", "(skip if -nobram)")) if (!nobram && check_label("bram", "(skip if -nobram)")) {
{
run("memory_bram -rules +/intel/common/brams.txt"); run("memory_bram -rules +/intel/common/brams.txt");
run("techmap -map +/intel/common/brams_map.v"); run("techmap -map +/intel/common/brams_map.v");
} }
if (check_label("fine")) if (check_label("fine")) {
{
run("opt -fast -mux_undef -undriven -fine -full"); run("opt -fast -mux_undef -undriven -fine -full");
run("memory_map"); run("memory_map");
run("opt -undriven -fine"); run("opt -undriven -fine");
@ -213,28 +208,26 @@ struct SynthIntelPass : public ScriptPass {
run("abc -markgroups -dff", "(only if -retime)"); run("abc -markgroups -dff", "(only if -retime)");
} }
if (check_label("map_luts")) if (check_label("map_luts")) {
{ if (family_opt == "a10gx" || family_opt == "cyclonev")
if(family_opt=="a10gx" || family_opt=="cyclonev")
run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : "")); run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
else else
run("abc -lut 4" + string(retime ? " -dff" : "")); run("abc -lut 4" + string(retime ? " -dff" : ""));
run("clean"); run("clean");
} }
if (check_label("map_cells")) if (check_label("map_cells")) {
{
if (!noiopads) if (!noiopads)
run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(unless -noiopads)"); run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(unless -noiopads)");
if(family_opt=="max10") if (family_opt == "max10")
run("techmap -map +/intel/max10/cells_map.v"); run("techmap -map +/intel/max10/cells_map.v");
else if(family_opt=="a10gx") else if (family_opt == "a10gx")
run("techmap -map +/intel/a10gx/cells_map.v"); run("techmap -map +/intel/a10gx/cells_map.v");
else if(family_opt=="cyclonev") else if (family_opt == "cyclonev")
run("techmap -map +/intel/cyclonev/cells_map.v"); run("techmap -map +/intel/cyclonev/cells_map.v");
else if(family_opt=="cyclone10") else if (family_opt == "cyclone10")
run("techmap -map +/intel/cyclone10/cells_map.v"); run("techmap -map +/intel/cyclone10/cells_map.v");
else if(family_opt=="cycloneiv") else if (family_opt == "cycloneiv")
run("techmap -map +/intel/cycloneiv/cells_map.v"); run("techmap -map +/intel/cycloneiv/cells_map.v");
else else
run("techmap -map +/intel/cycloneive/cells_map.v"); run("techmap -map +/intel/cycloneive/cells_map.v");
@ -242,24 +235,20 @@ struct SynthIntelPass : public ScriptPass {
run("clean -purge"); run("clean -purge");
} }
if (check_label("check")) if (check_label("check")) {
{
run("hierarchy -check"); run("hierarchy -check");
run("stat"); run("stat");
run("check -noinit"); run("check -noinit");
} }
if (check_label("vqm")) if (check_label("vqm")) {
{
if (!vout_file.empty() || help_mode) if (!vout_file.empty() || help_mode)
run(stringf("write_verilog -attr2comment -defparam -nohex -decimal -renameprefix syn_ %s", run(stringf("write_verilog -attr2comment -defparam -nohex -decimal -renameprefix syn_ %s",
help_mode ? "<file-name>" : vout_file.c_str())); help_mode ? "<file-name>" : vout_file.c_str()));
} }
if (check_label("vpr")) if (check_label("vpr")) {
{ if (!blif_file.empty() || help_mode) {
if (!blif_file.empty() || help_mode)
{
run(stringf("opt_clean -purge")); run(stringf("opt_clean -purge"));
run(stringf("write_blif %s", help_mode ? "<file-name>" : blif_file.c_str())); run(stringf("write_blif %s", help_mode ? "<file-name>" : blif_file.c_str()));
} }