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	Added SigSpec::has_const()
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					 2 changed files with 13 additions and 0 deletions
				
			
		|  | @ -1078,6 +1078,7 @@ void RTLIL::Module::check() | ||||||
| 
 | 
 | ||||||
| 	for (auto &it : connections_) { | 	for (auto &it : connections_) { | ||||||
| 		log_assert(it.first.size() == it.second.size()); | 		log_assert(it.first.size() == it.second.size()); | ||||||
|  | 		log_assert(!it.first.has_const()); | ||||||
| 		it.first.check(); | 		it.first.check(); | ||||||
| 		it.second.check(); | 		it.second.check(); | ||||||
| 	} | 	} | ||||||
|  | @ -2968,6 +2969,17 @@ bool RTLIL::SigSpec::is_fully_undef() const | ||||||
| 	return true; | 	return true; | ||||||
| } | } | ||||||
| 
 | 
 | ||||||
|  | bool RTLIL::SigSpec::has_const() const | ||||||
|  | { | ||||||
|  | 	cover("kernel.rtlil.sigspec.has_const"); | ||||||
|  | 
 | ||||||
|  | 	pack(); | ||||||
|  | 	for (auto it = chunks_.begin(); it != chunks_.end(); it++) | ||||||
|  | 		if (it->width > 0 && it->wire == NULL) | ||||||
|  | 			return true; | ||||||
|  | 	return false; | ||||||
|  | } | ||||||
|  | 
 | ||||||
| bool RTLIL::SigSpec::has_marked_bits() const | bool RTLIL::SigSpec::has_marked_bits() const | ||||||
| { | { | ||||||
| 	cover("kernel.rtlil.sigspec.has_marked_bits"); | 	cover("kernel.rtlil.sigspec.has_marked_bits"); | ||||||
|  |  | ||||||
|  | @ -672,6 +672,7 @@ public: | ||||||
| 	bool is_fully_const() const; | 	bool is_fully_const() const; | ||||||
| 	bool is_fully_def() const; | 	bool is_fully_def() const; | ||||||
| 	bool is_fully_undef() const; | 	bool is_fully_undef() const; | ||||||
|  | 	bool has_const() const; | ||||||
| 	bool has_marked_bits() const; | 	bool has_marked_bits() const; | ||||||
| 
 | 
 | ||||||
| 	bool as_bool() const; | 	bool as_bool() const; | ||||||
|  |  | ||||||
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