From 0eb93c80e6048668cf2b63fad97ea572c2aa998e Mon Sep 17 00:00:00 2001 From: Ethan Sifferman Date: Wed, 24 Sep 2025 20:50:47 -0700 Subject: [PATCH 1/2] added ifndef SIMLIB_NOCONNECT --- techlibs/common/simlib.v | 3 +++ 1 file changed, 3 insertions(+) diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 096df07b9..977b8bbf9 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -3219,6 +3219,8 @@ endmodule // -------------------------------------------------------- //* group wire +`ifndef SIMLIB_NOCONNECT + module \$connect (A, B); parameter WIDTH = 0; @@ -3230,6 +3232,7 @@ tran connect[WIDTH-1:0] (A, B); endmodule +`endif // -------------------------------------------------------- //* group wire module \$input_port (Y); From d5beb65d306116147f104f750089c660255c1eb5 Mon Sep 17 00:00:00 2001 From: Ethan Sifferman Date: Wed, 1 Oct 2025 10:19:25 -0700 Subject: [PATCH 2/2] added SIMLIB_VERILATOR_COMPAT --- techlibs/common/simlib.v | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 977b8bbf9..e0fb9fbfa 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -31,6 +31,14 @@ * */ +// If using Verilator, define SIMLIB_VERILATOR_COMPAT +`ifdef SIMLIB_VERILATOR_COMPAT + /* verilator lint_save */ + /* verilator lint_off DEFOVERRIDE */ + `define SIMLIB_NOCONNECT + /* verilator lint_restore */ +`endif + // -------------------------------------------------------- //* ver 2 //* title Bit-wise inverter