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opt_reduce: add test for constant $reduce_and/or not being zero width

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George Rennie 2024-09-25 16:28:41 +01:00
parent 023f029dcf
commit 0572f8806f
1 changed files with 14 additions and 0 deletions
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tests/opt/opt_reduce_andor.ys Normal file
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# Check that opt_reduce doesn't produce zero width $reduce_or/$reduce_and,
read_verilog <<EOT
module reduce_const(output wire o, output wire a);
wire [3:0] zero = 4'b0000;
wire [3:0] ones = 4'b1111;
assign o = |zero;
assign a = &ones;
endmodule
EOT
equiv_opt -assert opt_reduce
design -load postopt
select -assert-none r:A_WIDTH=0