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Some fixes to improve determinism

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This commit is contained in:
Clifford Wolf 2013-08-09 12:42:32 +02:00
parent d97782b848
commit 05483619f0
5 changed files with 41 additions and 32 deletions
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4
passes/opt/opt_clean.cc
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@ -35,7 +35,7 @@ static int count_rm_cells, count_rm_wires;
static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
{
SigMap assign_map(module);
std::set<RTLIL::Cell*> queue, unused;
std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> queue, unused;
SigSet<RTLIL::Cell*> wire2driver;
for (auto &it : module->cells) {
@ -66,7 +66,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
while (queue.size() > 0)
{
std::set<RTLIL::Cell*> new_queue;
std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> new_queue;
for (auto cell : queue)
unused.erase(cell);
for (auto cell : queue) {