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Add verific verilog test cases for blackboxes

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This commit is contained in:
Miodrag Milanovic 2024-12-06 16:13:25 +01:00
parent 7d4aff618f
commit 05398889ad
2 changed files with 58 additions and 0 deletions
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17
tests/verific/blackbox_empty.ys Normal file
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verific -sv <<EOF
module TEST_CELL(input clk, input a, input b, output reg c);
parameter PATH = "DEFAULT";
endmodule
EOF
verific -sv <<EOF
module top(input clk, input a, input b, output c, output d);
TEST_CELL #(.PATH("TEST")) test1(.clk(clk),.a(a),.b(1'b1),.c(c));
TEST_CELL #(.PATH("DEFAULT")) test2(.clk(clk),.a(a),.b(1'bx),.c(d));
endmodule
EOF
verific -import top
hierarchy -top top
stat
select -assert-count 2 t:TEST_CELL