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https://github.com/YosysHQ/yosys
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Add support for CEB, remove check on nusers
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parent
0166e02e78
commit
05282afc25
2 changed files with 33 additions and 16 deletions
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@ -1,14 +1,14 @@
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pattern xilinx_dsp
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state <SigBit> clock
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state <SigSpec> sigA sigffAmux sigB sigC sigM sigP
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state <IdString> ffAmuxAB ffMmuxAB postAddAB postAddMuxAB
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state <SigSpec> sigA sigffAmux sigB sigffBmux sigC sigM sigP
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state <IdString> ffAmuxAB ffBmuxAB ffMmuxAB postAddAB postAddMuxAB
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match dsp
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select dsp->type.in(\DSP48E1)
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endmatch
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code sigA sigffAmux sigB sigM
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code sigA sigffAmux sigB sigffBmux sigM
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sigA = port(dsp, \A);
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int i;
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for (i = GetSize(sigA)-1; i > 0; i--)
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@ -46,7 +46,6 @@ match ffA
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select param(ffA, \CLK_POLARITY).as_bool()
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filter GetSize(port(ffA, \Q)) >= GetSize(sigA)
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slice offset GetSize(port(ffA, \Q))
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filter offset+GetSize(sigA) <= GetSize(port(ffA, \Q)) && nusers(port(ffA, \Q).extract(offset, GetSize(sigA))) <= 3
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filter offset+GetSize(sigA) <= GetSize(port(ffA, \Q)) && port(ffA, \Q).extract(offset, GetSize(sigA)) == sigA
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optional
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endmatch
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@ -59,19 +58,19 @@ code sigA sigffAmux clock
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clock = port(ffA, \CLK).as_bit();
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if (nusers(sigA) == 3)
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sigffAmux = sigA;
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sigffAmux = sigA;
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sigA.replace(port(ffA, \Q), port(ffA, \D));
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}
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endcode
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match ffAmux
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if sigffAmux != SigSpec()
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if ffA
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select ffAmux->type.in($mux)
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choice <IdString> AB {\A, \B}
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index <SigSpec> port(ffAmux, \Y) === sigA
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index <SigSpec> port(ffAmux, AB) === sigffAmux
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set ffAmuxAB AB
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semioptional
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endmatch
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match ffB
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@ -85,7 +84,7 @@ match ffB
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optional
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endmatch
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code clock
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code sigB sigffBmux clock
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if (ffB) {
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for (auto b : port(ffB, \Q))
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if (b.wire->get_bool_attribute(\keep))
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@ -97,9 +96,22 @@ code clock
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reject;
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clock = c;
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sigffBmux = sigB;
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sigB.replace(port(ffB, \Q), port(ffB, \D));
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}
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endcode
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match ffBmux
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if ffB
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select ffBmux->type.in($mux)
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choice <IdString> AB {\A, \B}
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index <SigSpec> port(ffBmux, \Y) === sigB
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index <SigSpec> port(ffBmux, AB) === sigffBmux
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set ffBmuxAB AB
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semioptional
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endmatch
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match ffMmux
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select ffMmux->type.in($mux)
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select nusers(port(ffMmux, \Y)) == 2
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