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https://github.com/YosysHQ/yosys
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Add support for CEB, remove check on nusers
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parent
0166e02e78
commit
05282afc25
2 changed files with 33 additions and 16 deletions
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@ -34,6 +34,7 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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log("ffA: %s\n", log_id(st.ffA, "--"));
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log("ffAmux: %s\n", log_id(st.ffAmux, "--"));
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log("ffB: %s\n", log_id(st.ffB, "--"));
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log("ffBmux: %s\n", log_id(st.ffBmux, "--"));
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log("dsp: %s\n", log_id(st.dsp, "--"));
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log("ffM: %s\n", log_id(st.ffM, "--"));
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log("ffMmux: %s\n", log_id(st.ffMmux, "--"));
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@ -81,8 +82,6 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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SigSpec D = st.ffA->getPort("\\D");
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SigSpec Q = pm.sigmap(st.ffA->getPort("\\Q"));
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A.replace(Q, D);
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cell->setParam("\\AREG", 1);
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if (st.ffAmux) {
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SigSpec Y = st.ffAmux->getPort("\\Y");
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SigSpec AB = st.ffAmux->getPort(st.ffAmuxAB == "\\A" ? "\\B" : "\\A");
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@ -92,19 +91,25 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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else
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cell->setPort("\\CEA2", State::S1);
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cell->setPort("\\A", A);
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cell->setParam("\\AREG", 1);
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}
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if (st.ffB) {
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SigSpec B = cell->getPort("\\B");
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SigSpec D = st.ffB->getPort("\\D");
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SigSpec Q = st.ffB->getPort("\\Q");
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B.replace(Q, D);
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cell->setPort("\\B", B);
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cell->setParam("\\BREG", 1);
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if (st.ffB->type == "$dff")
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if (st.ffBmux) {
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SigSpec Y = st.ffBmux->getPort("\\Y");
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SigSpec AB = st.ffBmux->getPort(st.ffBmuxAB == "\\A" ? "\\B" : "\\A");
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B.replace(Y, AB);
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cell->setPort("\\CEB2", st.ffBmux->getPort("\\S"));
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}
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else
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cell->setPort("\\CEB2", State::S1);
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//else if (st.ffB->type == "$dffe")
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// cell->setPort("\\CEB2", st.ffB->getPort("\\EN"));
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else log_abort();
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cell->setPort("\\B", B);
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cell->setParam("\\BREG", 1);
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}
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if (st.ffM) {
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SigSpec D = st.ffM->getPort("\\D");
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