mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-28 03:15:50 +00:00
Code Activity

Merge remote-tracking branch 'origin/master' into xaig_dff

Browse source
This commit is contained in:
Eddie Hung 2019-07-10 16:05:41 -07:00
commit 052060f109
39 changed files with 1000 additions and 247 deletions
Download patch file Download diff file Expand all files Collapse all files

19
techlibs/xilinx/abc_xc7.box
View file

@ -3,17 +3,22 @@
# NB: Inputs/Outputs must be ordered alphabetically
# (with exceptions for carry in/out)
# F7BMUX slower than F7AMUX
# Average across F7[AB]MUX
# Inputs: I0 I1 S0
# Outputs: O
F7BMUX 1 1 3 1
217 223 296
F7MUX 1 1 3 1
204 208 286
# Inputs: I0 I1 S0
# Outputs: O
MUXF8 2 1 3 1
104 94 273
# Inputs: I0 I1 I2 I3 S0 S1
# Outputs: O
$__MUXF78 3 1 6 1
294 297 311 317 390 273
# CARRY4 + CARRY4_[ABCD]X
# Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI
# Outputs: O0 O1 O2 O3 CO0 CO1 CO2 CO3
@ -21,7 +26,7 @@ MUXF8 2 1 3 1
# input/output and the entire bus has been
# moved there overriding the otherwise
# alphabetical ordering)
CARRY4 3 1 10 8
CARRY4 4 1 10 8
482 - - - - 223 - - - 222
598 407 - - - 400 205 - - 334
584 556 537 - - 523 558 226 - 239
@ -34,21 +39,21 @@ CARRY4 3 1 10 8
# SLICEM/A6LUT
# Inputs: A0 A1 A2 A3 A4 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 WCLK WE
# Outputs: DPO SPO
RAM32X1D 4 0 13 2
RAM32X1D 5 0 13 2
- - - - - - 631 472 407 238 127 - -
631 472 407 238 127 - - - - - - - -
# SLICEM/A6LUT
# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
# Outputs: DPO SPO
RAM64X1D 5 0 15 2
RAM64X1D 6 0 15 2
- - - - - - - 642 631 472 407 238 127 - -
642 631 472 407 238 127 - - - - - - - - -
# SLICEM/A6LUT + F7[AB]MUX
# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
# Outputs: DPO SPO
RAM128X1D 6 0 17 2
RAM128X1D 7 0 17 2
- - - - - - - - 1009 998 839 774 605 494 450 - -
1047 1036 877 812 643 532 478 - - - - - - - - - -