diff --git a/passes/silimate/obs_clean.cc b/passes/silimate/obs_clean.cc
index 9bc3efea7..15ab8e205 100644
--- a/passes/silimate/obs_clean.cc
+++ b/passes/silimate/obs_clean.cc
@@ -39,46 +39,33 @@ void lhs2rhs_rhs2lhs(RTLIL::Module *module, SigMap &sigmap, dict<RTLIL::SigSpec,
 	for (auto it = module->connections().begin(); it != module->connections().end(); ++it) {
 		RTLIL::SigSpec lhs = it->first;
 		RTLIL::SigSpec rhs = it->second;
-		if (lhs.is_chunk()) {
-			std::cout << "lhs ischunck: " << lhs.size() << std::endl;
-		} else {
-			std::cout << "lhs isnotchunck: " << lhs.size() << std::endl;
-		}
-		if (rhs.is_chunk()) {
-			std::cout << "rhs ischunck: " << rhs.size() << std::endl;
-		} else {
-			std::cout << "rhs isnotchunck" << std::endl;
-		}
 		if (!lhs.is_chunk()) {
 			std::vector<SigSpec> lhsBits;
 			for (int i = 0; i < lhs.size(); i++) {
 				SigSpec bit_sig = lhs.extract(i, 1);
 				lhsBits.push_back(bit_sig);
-				std::cout << "li:" << i << std::endl;
 			}
 			std::vector<SigSpec> rhsBits;
 			for (int i = 0; i < rhs.size(); i++) {
 				SigSpec bit_sig = rhs.extract(i, 1);
 				rhsBits.push_back(bit_sig);
-				std::cout << "ri:" << i << std::endl;
 			}
 
 			for (uint32_t i = 0; i < lhsBits.size(); i++) {
 				if (i < rhsBits.size()) {
-					std::cout << "lri:" << i << std::endl;
 					rhsSig2LhsSig[sigmap(rhsBits[i])].insert(sigmap(lhsBits[i]));
-					lhsSig2rhsSig[sigmap(lhsBits[i])] = sigmap(rhsBits[i]);
-				}	
+					lhsSig2rhsSig[lhsBits[i]] = sigmap(rhsBits[i]);
+				}
 			}
 		} else {
 			rhsSig2LhsSig[sigmap(rhs)].insert(sigmap(lhs));
-			lhsSig2rhsSig[sigmap(lhs)] = sigmap(rhs);
+			lhsSig2rhsSig[lhs] = sigmap(rhs);
 		}
 	}
 }
 
 // Collect transitive fanin of a sig
-void collectTransitiveFanin(RTLIL::SigSpec &sig, SigMap& sigmap, dict<RTLIL::SigSpec, std::set<Cell *>> &sig2CellsInFanin,
+void collectTransitiveFanin(RTLIL::SigSpec &sig, SigMap &sigmap, dict<RTLIL::SigSpec, std::set<Cell *>> &sig2CellsInFanin,
 			    dict<RTLIL::SigSpec, RTLIL::SigSpec> &lhsSig2RhsSig, std::set<Cell *> &visitedCells,
 			    std::set<RTLIL::SigSpec> &visitedSigSpec)
 {
@@ -100,19 +87,17 @@ void collectTransitiveFanin(RTLIL::SigSpec &sig, SigMap& sigmap, dict<RTLIL::Sig
 					collectTransitiveFanin(actual, sigmap, sig2CellsInFanin, lhsSig2RhsSig, visitedCells, visitedSigSpec);
 					for (int i = 0; i < actual.size(); i++) {
 						SigSpec bit_sig = actual.extract(i, 1);
-						collectTransitiveFanin(bit_sig, sigmap, sig2CellsInFanin, lhsSig2RhsSig, visitedCells, visitedSigSpec);
+						collectTransitiveFanin(bit_sig, sigmap, sig2CellsInFanin, lhsSig2RhsSig, visitedCells,
+								       visitedSigSpec);
 					}
 				}
 			}
 		}
 	}
-	std::cout << "HERE\n";
 	if (lhsSig2RhsSig.count(sigmap(sig))) {
-		std::cout << "THERE\n";
 		RTLIL::SigSpec rhs = lhsSig2RhsSig[sigmap(sig)];
 		collectTransitiveFanin(rhs, sigmap, sig2CellsInFanin, lhsSig2RhsSig, visitedCells, visitedSigSpec);
 		for (int i = 0; i < rhs.size(); i++) {
-			std::cout << "THERE: " << i << "\n";
 			SigSpec bit_sig = rhs.extract(i, 1);
 			collectTransitiveFanin(bit_sig, sigmap, sig2CellsInFanin, lhsSig2RhsSig, visitedCells, visitedSigSpec);
 		}
@@ -120,7 +105,7 @@ void collectTransitiveFanin(RTLIL::SigSpec &sig, SigMap& sigmap, dict<RTLIL::Sig
 }
 
 // Only keep the cells and wires that are visited using the transitive fanin reached from output ports or keep signals
-void observabilityClean(RTLIL::Module *module, SigMap& sigmap, dict<RTLIL::SigSpec, std::set<Cell *>> &sig2CellsInFanin,
+void observabilityClean(RTLIL::Module *module, SigMap &sigmap, dict<RTLIL::SigSpec, std::set<Cell *>> &sig2CellsInFanin,
 			dict<RTLIL::SigSpec, RTLIL::SigSpec> &lhsSig2RhsSig)
 {
 	if (module->get_bool_attribute(ID::keep))
@@ -147,16 +132,6 @@ void observabilityClean(RTLIL::Module *module, SigMap& sigmap, dict<RTLIL::SigSp
 		if (w && (!w->port_output) && (!w->get_bool_attribute(ID::keep))) {
 			continue;
 		}
-		if (po.is_chunk()) {
-			std::cout << "po ischunck" << std::endl;
-		} else {
-			std::cout << "po isnotchunck" << std::endl;
-		}
-		if (w)
-		  std::cout << "Name: " << w->name.c_str() << std::endl;
-		else 
-			 std::cout << "No Name: " << std::endl;
-		std::cout << "PO size: " << po.size() << std::endl;
 		collectTransitiveFanin(po, sigmap, sig2CellsInFanin, lhsSig2RhsSig, visitedCells, visitedSigSpec);
 		for (int i = 0; i < po.size(); i++) {
 			SigSpec bit_sig = po.extract(i, 1);
@@ -164,7 +139,7 @@ void observabilityClean(RTLIL::Module *module, SigMap& sigmap, dict<RTLIL::SigSp
 		}
 	}
 
-	pool<RTLIL::SigSig> newConnections;
+	std::vector<RTLIL::SigSig> newConnections;
 	for (auto it = module->connections().begin(); it != module->connections().end(); ++it) {
 		RTLIL::SigSpec lhs = it->first;
 		RTLIL::SigSpec sigmaplhs = sigmap(lhs);
@@ -172,18 +147,16 @@ void observabilityClean(RTLIL::Module *module, SigMap& sigmap, dict<RTLIL::SigSp
 			lhs = sigmaplhs;
 		}
 		if (visitedSigSpec.count(lhs)) {
-			newConnections.insert(*it);
-			std::cout << "New connection\n";
+			newConnections.push_back(*it);
 		} else {
 			for (int i = 0; i < lhs.size(); i++) {
 				SigSpec bit_sig = lhs.extract(i, 1);
 				RTLIL::SigSpec sigmapbit_sig = sigmap(bit_sig);
-				//if (!sigmapbit_sig.is_fully_const()) {
-					bit_sig = sigmapbit_sig;
+				// if (!sigmapbit_sig.is_fully_const()) {
+				bit_sig = sigmapbit_sig;
 				//}
 				if (visitedSigSpec.count(bit_sig)) {
-					newConnections.insert(*it);
-					std::cout << "New connection\n";
+					newConnections.push_back(*it);
 					break;
 				}
 			}