From 04d2f55bec69d551d344d7ba5d3ec25535b8a97e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 27 Nov 2023 18:28:10 +0100 Subject: [PATCH] fixup! add qlf_k6n10f architecture + bram inference --- .../quicklogic/qlf_k6n10f/libmap_brams_map.v | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v b/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v index 7a6a1c982..f4f4420c1 100644 --- a/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v +++ b/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v @@ -1,3 +1,19 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + module \$__QLF_TDP36K (PORT_A_CLK, PORT_A_ADDR, PORT_A_WR_DATA, PORT_A_WR_EN, PORT_A_WR_BE, PORT_A_CLK_EN, PORT_A_RD_DATA, PORT_B_CLK, PORT_B_ADDR, PORT_B_WR_DATA, PORT_B_WR_EN, PORT_B_WR_BE, PORT_B_CLK_EN, PORT_B_RD_DATA);