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Merge pull request #5399 from povik/opt_hier-bug
opt_hier: Fix two optimizations conflicting
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commit
04c7013f0e
2 changed files with 39 additions and 7 deletions
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@ -144,12 +144,12 @@ struct ModuleIndex {
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}
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if (nunused > 0) {
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log("Disconnected %d input bits of instance '%s' of '%s' in '%s'\n",
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log("Disconnected %d input bits of instance '%s' (type '%s') in '%s'\n",
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nunused, log_id(instantiation), log_id(instantiation->type), log_id(parent.module));
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changed = true;
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}
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if (nconstants > 0) {
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log("Substituting constant for %d output bits of instance '%s' of '%s' in '%s'\n",
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log("Substituting constant for %d output bits of instance '%s' (type '%s') in '%s'\n",
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nconstants, log_id(instantiation), log_id(instantiation->type), log_id(parent.module));
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changed = true;
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}
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@ -310,7 +310,7 @@ struct UsageData {
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refine_tie_togethers(inputs);
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}
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bool apply_changes() {
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bool apply_changes(ModuleIndex &index) {
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bool did_something = false;
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if (module->get_blackbox_attribute()) {
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@ -374,8 +374,16 @@ struct UsageData {
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// Propagate tied-together inputs
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dict<SigBit, SigBit> ties;
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for (auto group : tie_together_inputs) {
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for (int i = 1; i < group.size(); i++)
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ties[group[i]] = group[0];
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// Only consider used inputs for a tie-together group.
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// ModuleIndex::apply_changes might have disconnected
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// unused inputs.
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SigSpec filtered_group;
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for (auto bit : group) {
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if (index.used.check(bit))
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filtered_group.append(bit);
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}
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for (int i = 1; i < filtered_group.size(); i++)
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ties[filtered_group[i]] = filtered_group[0];
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}
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SigPool applied_ties;
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auto ties_rewrite = [&](SigSpec &signal) {
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@ -449,12 +457,13 @@ struct OptHierPass : Pass {
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bool did_something = false;
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for (auto module : d->selected_modules(RTLIL::SELECT_WHOLE_ONLY, RTLIL::SB_UNBOXED_CMDERR)) {
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ModuleIndex &parent_index = indices.at(module->name);
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if (usage_datas.count(module->name)) {
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log_debug("Applying usage data changes to %s\n", log_id(module));
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did_something |= usage_datas.at(module->name).apply_changes();
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did_something |= usage_datas.at(module->name).apply_changes(parent_index);
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}
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ModuleIndex &parent_index = indices.at(module->name);
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for (auto cell : module->cells()) {
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if (indices.count(cell->type)) {
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log_debug("Applying changes to instance %s of %s in %s\n", log_id(cell), log_id(cell->type), log_id(module));
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23
tests/opt/bug5398.ys
Normal file
23
tests/opt/bug5398.ys
Normal file
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@ -0,0 +1,23 @@
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read_verilog <<EOF
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module tag_2x4(
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input R0_clk,
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input W0_clk,
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output x,
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);
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assign x = !W0_clk;
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endmodule
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module top(input clock, output x, output flag);
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tag_2x4 tag_ext(
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.R0_clk (clock),
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.W0_clk (clock),
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.x (x)
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);
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assign flag = x ^ clock;
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endmodule
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EOF
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hierarchy -top top
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opt_hier
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flatten
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sat -verify -prove flag 1
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