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No implicit conversion from IdString to anything else

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This commit is contained in:
Clifford Wolf 2014-08-02 18:58:40 +02:00
parent 768eb846c4
commit 04727c7e0f
16 changed files with 37 additions and 37 deletions
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2
backends/blif/blif.cc
View file

@ -363,7 +363,7 @@ struct BlifBackend : public Backend {
if (top_module_name.empty()) if (top_module_name.empty())
for (auto & mod_it:design->modules_) for (auto & mod_it:design->modules_)
if (mod_it.second->get_bool_attribute("\\top")) if (mod_it.second->get_bool_attribute("\\top"))
top_module_name = mod_it.first; top_module_name = mod_it.first.str();
fprintf(f, "# Generated by %s\n", yosys_version_str); fprintf(f, "# Generated by %s\n", yosys_version_str);

2
backends/btor/btor.cc
View file

@ -968,7 +968,7 @@ struct BtorBackend : public Backend {
if (top_module_name.empty()) if (top_module_name.empty())
for (auto & mod_it:design->modules_) for (auto & mod_it:design->modules_)
if (mod_it.second->get_bool_attribute("\\top")) if (mod_it.second->get_bool_attribute("\\top"))
top_module_name = mod_it.first; top_module_name = mod_it.first.str();
fprintf(f, "; Generated by %s\n", yosys_version_str); fprintf(f, "; Generated by %s\n", yosys_version_str);
fprintf(f, "; %s developed and maintained by Clifford Wolf <clifford@clifford.at>\n", yosys_version_str); fprintf(f, "; %s developed and maintained by Clifford Wolf <clifford@clifford.at>\n", yosys_version_str);

4
backends/edif/edif.cc
View file

@ -126,7 +126,7 @@ struct EdifBackend : public Backend {
if (top_module_name.empty()) if (top_module_name.empty())
for (auto & mod_it:design->modules_) for (auto & mod_it:design->modules_)
if (mod_it.second->get_bool_attribute("\\top")) if (mod_it.second->get_bool_attribute("\\top"))
top_module_name = mod_it.first; top_module_name = mod_it.first.str();
for (auto module_it : design->modules_) for (auto module_it : design->modules_)
{ {
@ -135,7 +135,7 @@ struct EdifBackend : public Backend {
continue; continue;
if (top_module_name.empty()) if (top_module_name.empty())
top_module_name = module->name; top_module_name = module->name.str();
if (module->processes.size() != 0) if (module->processes.size() != 0)
log_error("Found unmapped processes in module %s: unmapped processes are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name)); log_error("Found unmapped processes in module %s: unmapped processes are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name));

2
backends/spice/spice.cc
View file

@ -172,7 +172,7 @@ struct SpiceBackend : public Backend {
if (top_module_name.empty()) if (top_module_name.empty())
for (auto & mod_it:design->modules_) for (auto & mod_it:design->modules_)
if (mod_it.second->get_bool_attribute("\\top")) if (mod_it.second->get_bool_attribute("\\top"))
top_module_name = mod_it.first; top_module_name = mod_it.first.str();
fprintf(f, "* SPICE netlist generated by %s\n", yosys_version_str); fprintf(f, "* SPICE netlist generated by %s\n", yosys_version_str);
fprintf(f, "\n"); fprintf(f, "\n");

2
kernel/log.cc
View file

@ -215,7 +215,7 @@ const char *log_signal(const RTLIL::SigSpec &sig, bool autoint)
const char *log_id(RTLIL::IdString str) const char *log_id(RTLIL::IdString str)
{ {
const char *p = str; const char *p = str.c_str();
log_assert(RTLIL::IdString::global_refcount_storage_[str.index_] > 1); log_assert(RTLIL::IdString::global_refcount_storage_[str.index_] > 1);
if (p[0] == '\\' && p[1] != '$' && p[1] != 0) if (p[0] == '\\' && p[1] != '$' && p[1] != 0)
return p+1; return p+1;

4
kernel/register.cc
View file

@ -240,7 +240,7 @@ void Pass::call_on_selection(RTLIL::Design *design, const RTLIL::Selection &sele
void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::string command) void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::string command)
{ {
std::string backup_selected_active_module = design->selected_active_module; std::string backup_selected_active_module = design->selected_active_module;
design->selected_active_module = module->name; design->selected_active_module = module->name.str();
design->selection_stack.push_back(RTLIL::Selection(false)); design->selection_stack.push_back(RTLIL::Selection(false));
design->selection_stack.back().select(module); design->selection_stack.back().select(module);
@ -253,7 +253,7 @@ void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::str
void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::vector<std::string> args) void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::vector<std::string> args)
{ {
std::string backup_selected_active_module = design->selected_active_module; std::string backup_selected_active_module = design->selected_active_module;
design->selected_active_module = module->name; design->selected_active_module = module->name.str();
design->selection_stack.push_back(RTLIL::Selection(false)); design->selection_stack.push_back(RTLIL::Selection(false));
design->selection_stack.back().select(module); design->selection_stack.back().select(module);

28
kernel/rtlil.cc
View file

@ -286,7 +286,7 @@ void RTLIL::Design::check()
for (auto &it : modules_) { for (auto &it : modules_) {
log_assert(this == it.second->design); log_assert(this == it.second->design);
log_assert(it.first == it.second->name); log_assert(it.first == it.second->name);
log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); log_assert(!it.first.empty());
it.second->check(); it.second->check();
} }
#endif #endif
@ -499,7 +499,7 @@ namespace {
void check() void check()
{ {
if (cell->type[0] != '$' || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" || if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" ||
cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:") cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
return; return;
@ -818,38 +818,38 @@ void RTLIL::Module::check()
for (auto &it : wires_) { for (auto &it : wires_) {
log_assert(this == it.second->module); log_assert(this == it.second->module);
log_assert(it.first == it.second->name); log_assert(it.first == it.second->name);
log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); log_assert(!it.first.empty());
log_assert(it.second->width >= 0); log_assert(it.second->width >= 0);
log_assert(it.second->port_id >= 0); log_assert(it.second->port_id >= 0);
for (auto &it2 : it.second->attributes) { for (auto &it2 : it.second->attributes) {
log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$')); log_assert(!it2.first.empty());
} }
} }
for (auto &it : memories) { for (auto &it : memories) {
log_assert(it.first == it.second->name); log_assert(it.first == it.second->name);
log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); log_assert(!it.first.empty());
log_assert(it.second->width >= 0); log_assert(it.second->width >= 0);
log_assert(it.second->size >= 0); log_assert(it.second->size >= 0);
for (auto &it2 : it.second->attributes) { for (auto &it2 : it.second->attributes) {
log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$')); log_assert(!it2.first.empty());
} }
} }
for (auto &it : cells_) { for (auto &it : cells_) {
log_assert(this == it.second->module); log_assert(this == it.second->module);
log_assert(it.first == it.second->name); log_assert(it.first == it.second->name);
log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); log_assert(!it.first.empty());
log_assert(it.second->type.size() > 0 && (it.second->type[0] == '\\' || it.second->type[0] == '$')); log_assert(!it.second->type.empty());
for (auto &it2 : it.second->connections()) { for (auto &it2 : it.second->connections()) {
log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$')); log_assert(!it2.first.empty());
it2.second.check(); it2.second.check();
} }
for (auto &it2 : it.second->attributes) { for (auto &it2 : it.second->attributes) {
log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$')); log_assert(!it2.first.empty());
} }
for (auto &it2 : it.second->parameters) { for (auto &it2 : it.second->parameters) {
log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$')); log_assert(!it2.first.empty());
} }
InternalCellChecker checker(this, it.second); InternalCellChecker checker(this, it.second);
checker.check(); checker.check();
@ -857,7 +857,7 @@ void RTLIL::Module::check()
for (auto &it : processes) { for (auto &it : processes) {
log_assert(it.first == it.second->name); log_assert(it.first == it.second->name);
log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); log_assert(!it.first.empty());
// FIXME: More checks here.. // FIXME: More checks here..
} }
@ -868,7 +868,7 @@ void RTLIL::Module::check()
} }
for (auto &it : attributes) { for (auto &it : attributes) {
log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); log_assert(!it.first.empty());
} }
#endif #endif
} }
@ -1597,7 +1597,7 @@ void RTLIL::Cell::check()
void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
{ {
if (type[0] != '$' || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" || if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" ||
type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:") type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
return; return;

8
kernel/rtlil.h
View file

@ -166,10 +166,6 @@ namespace RTLIL
return global_id_storage_.at(index_); return global_id_storage_.at(index_);
} }
operator const char*() const {
return global_id_storage_.at(index_);
}
std::string str() const { std::string str() const {
return std::string(global_id_storage_.at(index_)); return std::string(global_id_storage_.at(index_));
} }
@ -193,6 +189,10 @@ namespace RTLIL
return c_str()[i]; return c_str()[i];
} }
char operator[](size_t i) const {
return c_str()[i];
}
std::string substr(size_t pos = 0, size_t len = std::string::npos) const { std::string substr(size_t pos = 0, size_t len = std::string::npos) const {
if (len == std::string::npos || len >= strlen(c_str() + pos)) if (len == std::string::npos || len >= strlen(c_str() + pos))
return std::string(c_str() + pos); return std::string(c_str() + pos);

2
passes/abc/abc.cc
View file

@ -303,7 +303,7 @@ static void handle_loops()
id1 = id2; id1 = id2;
else if (edges[id1].size() > edges[id2].size()) else if (edges[id1].size() > edges[id2].size())
continue; continue;
else if (w1->name > w2->name) else if (w2->name < w1->name)
id1 = id2; id1 = id2;
} }

2
passes/cmds/design.cc
View file

@ -192,7 +192,7 @@ struct DesignPass : public Pass {
for (auto mod : copy_src_modules) for (auto mod : copy_src_modules)
{ {
std::string trg_name = as_name.empty() ? std::string(mod->name) : RTLIL::escape_id(as_name); std::string trg_name = as_name.empty() ? mod->name.str() : RTLIL::escape_id(as_name);
if (copy_to_design->modules_.count(trg_name)) if (copy_to_design->modules_.count(trg_name))
delete copy_to_design->modules_.at(trg_name); delete copy_to_design->modules_.at(trg_name);

4
passes/cmds/select.cc
View file

@ -1080,7 +1080,7 @@ struct SelectPass : public Pass {
RTLIL::IdString mod_name = RTLIL::escape_id(args[++argidx]); RTLIL::IdString mod_name = RTLIL::escape_id(args[++argidx]);
if (design->modules_.count(mod_name) == 0) if (design->modules_.count(mod_name) == 0)
log_cmd_error("No such module: %s\n", id2cstr(mod_name)); log_cmd_error("No such module: %s\n", id2cstr(mod_name));
design->selected_active_module = mod_name; design->selected_active_module = mod_name.str();
got_module = true; got_module = true;
continue; continue;
} }
@ -1304,7 +1304,7 @@ struct CdPass : public Pass {
if (design->modules_.count(design->selected_active_module) > 0) if (design->modules_.count(design->selected_active_module) > 0)
module = design->modules_.at(design->selected_active_module); module = design->modules_.at(design->selected_active_module);
if (module != NULL && module->cells_.count(modname) > 0) if (module != NULL && module->cells_.count(modname) > 0)
modname = module->cells_.at(modname)->type; modname = module->cells_.at(modname)->type.str();
} }
if (design->modules_.count(modname) > 0) { if (design->modules_.count(modname) > 0) {

2
passes/cmds/show.cc
View file

@ -322,7 +322,7 @@ struct ShowWorker
else if (it.second->port_output) else if (it.second->port_output)
all_sinks.insert(stringf("n%d", id2num(it.first))); all_sinks.insert(stringf("n%d", id2num(it.first)));
} else { } else {
wires_on_demand[stringf("n%d", id2num(it.first))] = it.first; wires_on_demand[stringf("n%d", id2num(it.first))] = it.first.str();
} }
} }

2
passes/fsm/fsm_export.cc
View file

@ -61,7 +61,7 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st
kiss_name.assign(attr_it->second.decode_string()); kiss_name.assign(attr_it->second.decode_string());
} }
else { else {
kiss_name.assign(module->name); kiss_name.assign(module->name.str());
kiss_name.append('-' + cell->name.str() + ".kiss2"); kiss_name.append('-' + cell->name.str() + ".kiss2");
} }

2
passes/memory/memory_collect.cc
View file

@ -126,7 +126,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
} }
std::stringstream sstr; std::stringstream sstr;
sstr << "$mem$" << memory->name << "$" << (autoidx++); sstr << "$mem$" << memory->name.str() << "$" << (autoidx++);
RTLIL::Cell *mem = module->addCell(sstr.str(), "$mem"); RTLIL::Cell *mem = module->addCell(sstr.str(), "$mem");
mem->parameters["\\MEMID"] = RTLIL::Const(memory->name.str()); mem->parameters["\\MEMID"] = RTLIL::Const(memory->name.str());

4
passes/techmap/extract.cc
View file

@ -240,8 +240,8 @@ namespace
if (sig_bit_ref.count(bit) == 0) { if (sig_bit_ref.count(bit) == 0) {
bit_ref_t &bit_ref = sig_bit_ref[bit]; bit_ref_t &bit_ref = sig_bit_ref[bit];
bit_ref.cell = cell->name; bit_ref.cell = cell->name.str();
bit_ref.port = conn.first; bit_ref.port = conn.first.str();
bit_ref.bit = i; bit_ref.bit = i;
} }

2
passes/techmap/techmap.cc
View file

@ -155,7 +155,7 @@ struct TechmapWorker
if (!flatten_mode) if (!flatten_mode)
for (auto &it : tpl->cells_) for (auto &it : tpl->cells_)
if (it.first == "\\_TECHMAP_REPLACE_") { if (it.first == "\\_TECHMAP_REPLACE_") {
orig_cell_name = cell->name; orig_cell_name = cell->name.str();
module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str()); module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
break; break;
} }