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No implicit conversion from IdString to anything else

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This commit is contained in:
Clifford Wolf 2014-08-02 18:58:40 +02:00
parent 768eb846c4
commit 04727c7e0f
16 changed files with 37 additions and 37 deletions
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2
passes/abc/abc.cc
View file

@ -303,7 +303,7 @@ static void handle_loops()
id1 = id2;
else if (edges[id1].size() > edges[id2].size())
continue;
else if (w1->name > w2->name)
else if (w2->name < w1->name)
id1 = id2;
}

2
passes/cmds/design.cc
View file

@ -192,7 +192,7 @@ struct DesignPass : public Pass {
for (auto mod : copy_src_modules)
{
std::string trg_name = as_name.empty() ? std::string(mod->name) : RTLIL::escape_id(as_name);
std::string trg_name = as_name.empty() ? mod->name.str() : RTLIL::escape_id(as_name);
if (copy_to_design->modules_.count(trg_name))
delete copy_to_design->modules_.at(trg_name);

4
passes/cmds/select.cc
View file

@ -1080,7 +1080,7 @@ struct SelectPass : public Pass {
RTLIL::IdString mod_name = RTLIL::escape_id(args[++argidx]);
if (design->modules_.count(mod_name) == 0)
log_cmd_error("No such module: %s\n", id2cstr(mod_name));
design->selected_active_module = mod_name;
design->selected_active_module = mod_name.str();
got_module = true;
continue;
}
@ -1304,7 +1304,7 @@ struct CdPass : public Pass {
if (design->modules_.count(design->selected_active_module) > 0)
module = design->modules_.at(design->selected_active_module);
if (module != NULL && module->cells_.count(modname) > 0)
modname = module->cells_.at(modname)->type;
modname = module->cells_.at(modname)->type.str();
}
if (design->modules_.count(modname) > 0) {

2
passes/cmds/show.cc
View file

@ -322,7 +322,7 @@ struct ShowWorker
else if (it.second->port_output)
all_sinks.insert(stringf("n%d", id2num(it.first)));
} else {
wires_on_demand[stringf("n%d", id2num(it.first))] = it.first;
wires_on_demand[stringf("n%d", id2num(it.first))] = it.first.str();
}
}

2
passes/fsm/fsm_export.cc
View file

@ -61,7 +61,7 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st
kiss_name.assign(attr_it->second.decode_string());
}
else {
kiss_name.assign(module->name);
kiss_name.assign(module->name.str());
kiss_name.append('-' + cell->name.str() + ".kiss2");
}

2
passes/memory/memory_collect.cc
View file

@ -126,7 +126,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
}
std::stringstream sstr;
sstr << "$mem$" << memory->name << "$" << (autoidx++);
sstr << "$mem$" << memory->name.str() << "$" << (autoidx++);
RTLIL::Cell *mem = module->addCell(sstr.str(), "$mem");
mem->parameters["\\MEMID"] = RTLIL::Const(memory->name.str());

4
passes/techmap/extract.cc
View file

@ -240,8 +240,8 @@ namespace
if (sig_bit_ref.count(bit) == 0) {
bit_ref_t &bit_ref = sig_bit_ref[bit];
bit_ref.cell = cell->name;
bit_ref.port = conn.first;
bit_ref.cell = cell->name.str();
bit_ref.port = conn.first.str();
bit_ref.bit = i;
}

2
passes/techmap/techmap.cc
View file

@ -155,7 +155,7 @@ struct TechmapWorker
if (!flatten_mode)
for (auto &it : tpl->cells_)
if (it.first == "\\_TECHMAP_REPLACE_") {
orig_cell_name = cell->name;
orig_cell_name = cell->name.str();
module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
break;
}