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Use State::S{0,1}

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This commit is contained in:
Eddie Hung 2019-08-06 16:22:47 -07:00
parent 3486235338
commit 046e1a5214
10 changed files with 19 additions and 19 deletions
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2
passes/techmap/simplemap.cc
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@ -185,7 +185,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell
}
if (sig.size() == 0)
sig = RTLIL::SigSpec(0, 1);
sig = State::S0;
}
void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)