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Use State::S{0,1}

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This commit is contained in:
Eddie Hung 2019-08-06 16:22:47 -07:00
parent 3486235338
commit 046e1a5214
10 changed files with 19 additions and 19 deletions
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2
passes/memory/memory_map.cc
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@ -301,7 +301,7 @@ struct MemoryMapWorker
RTLIL::Wire *w = w_seladdr;
if (wr_bit != RTLIL::SigSpec(1, 1))
if (wr_bit != State::S1)
{
RTLIL::Cell *c = module->addCell(genid(cell->name, "$wren", i, "", j, "", wr_offset), "$and");
c->parameters["\\A_SIGNED"] = RTLIL::Const(0);