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Use State::S{0,1}

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This commit is contained in:
Eddie Hung 2019-08-06 16:22:47 -07:00
parent 3486235338
commit 046e1a5214
10 changed files with 19 additions and 19 deletions
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4
passes/fsm/fsm_map.cc
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@ -133,7 +133,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
cases_vector.append(and_sig);
break;
case 0:
cases_vector.append(RTLIL::SigSpec(1, 1));
cases_vector.append(State::S1);
break;
default:
log_abort();
@ -150,7 +150,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
} else if (cases_vector.size() == 1) {
module->connect(RTLIL::SigSig(output, cases_vector));
} else {
module->connect(RTLIL::SigSig(output, RTLIL::SigSpec(0, 1)));
module->connect(RTLIL::SigSig(output, State::S0));
}
}