mirror of
https://github.com/YosysHQ/yosys
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Rip out unused functions in abc9
This commit is contained in:
Eddie Hung
parent
e9df9a466a
commit
045f7763ae
1 changed files with 61 additions and 416 deletions
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@ -117,216 +117,6 @@ bool clk_polarity, en_polarity;
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RTLIL::SigSpec clk_sig, en_sig;
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dict<int, std::string> pi_map, po_map;
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int map_signal(RTLIL::SigBit bit, gate_type_t gate_type = G(NONE), int in1 = -1, int in2 = -1, int in3 = -1, int in4 = -1)
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{
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assign_map.apply(bit);
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if (signal_map.count(bit) == 0) {
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gate_t gate;
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gate.id = signal_list.size();
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gate.type = G(NONE);
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gate.in1 = -1;
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gate.in2 = -1;
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gate.in3 = -1;
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gate.in4 = -1;
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gate.is_port = false;
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gate.bit = bit;
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if (signal_init.count(bit))
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gate.init = signal_init.at(bit);
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else
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gate.init = State::Sx;
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signal_list.push_back(gate);
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signal_map[bit] = gate.id;
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}
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gate_t &gate = signal_list[signal_map[bit]];
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if (gate_type != G(NONE))
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gate.type = gate_type;
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if (in1 >= 0)
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gate.in1 = in1;
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if (in2 >= 0)
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gate.in2 = in2;
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if (in3 >= 0)
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gate.in3 = in3;
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if (in4 >= 0)
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gate.in4 = in4;
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return gate.id;
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}
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void mark_port(RTLIL::SigSpec sig)
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{
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for (auto &bit : assign_map(sig))
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if (bit.wire != NULL && signal_map.count(bit) > 0)
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signal_list[signal_map[bit]].is_port = true;
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}
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void extract_cell(RTLIL::Cell *cell, bool keepff)
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{
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if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_")
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{
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if (clk_polarity != (cell->type == "$_DFF_P_"))
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return;
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if (clk_sig != assign_map(cell->getPort("\\C")))
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return;
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if (GetSize(en_sig) != 0)
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return;
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goto matching_dff;
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}
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if (cell->type == "$_DFFE_NN_" || cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_")
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{
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if (clk_polarity != (cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_"))
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return;
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if (en_polarity != (cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PP_"))
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return;
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if (clk_sig != assign_map(cell->getPort("\\C")))
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return;
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if (en_sig != assign_map(cell->getPort("\\E")))
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return;
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goto matching_dff;
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}
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if (0) {
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matching_dff:
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RTLIL::SigSpec sig_d = cell->getPort("\\D");
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RTLIL::SigSpec sig_q = cell->getPort("\\Q");
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if (keepff)
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for (auto &c : sig_q.chunks())
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if (c.wire != NULL)
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c.wire->attributes["\\keep"] = 1;
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assign_map.apply(sig_d);
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assign_map.apply(sig_q);
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map_signal(sig_q, G(FF), map_signal(sig_d));
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module->remove(cell);
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return;
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}
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if (cell->type.in("$_BUF_", "$_NOT_"))
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{
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RTLIL::SigSpec sig_a = cell->getPort("\\A");
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RTLIL::SigSpec sig_y = cell->getPort("\\Y");
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assign_map.apply(sig_a);
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assign_map.apply(sig_y);
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map_signal(sig_y, cell->type == "$_BUF_" ? G(BUF) : G(NOT), map_signal(sig_a));
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module->remove(cell);
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return;
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}
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if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_"))
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{
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RTLIL::SigSpec sig_a = cell->getPort("\\A");
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RTLIL::SigSpec sig_b = cell->getPort("\\B");
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RTLIL::SigSpec sig_y = cell->getPort("\\Y");
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assign_map.apply(sig_a);
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assign_map.apply(sig_b);
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assign_map.apply(sig_y);
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int mapped_a = map_signal(sig_a);
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int mapped_b = map_signal(sig_b);
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if (cell->type == "$_AND_")
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map_signal(sig_y, G(AND), mapped_a, mapped_b);
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else if (cell->type == "$_NAND_")
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map_signal(sig_y, G(NAND), mapped_a, mapped_b);
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else if (cell->type == "$_OR_")
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map_signal(sig_y, G(OR), mapped_a, mapped_b);
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else if (cell->type == "$_NOR_")
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map_signal(sig_y, G(NOR), mapped_a, mapped_b);
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else if (cell->type == "$_XOR_")
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map_signal(sig_y, G(XOR), mapped_a, mapped_b);
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else if (cell->type == "$_XNOR_")
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map_signal(sig_y, G(XNOR), mapped_a, mapped_b);
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else if (cell->type == "$_ANDNOT_")
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map_signal(sig_y, G(ANDNOT), mapped_a, mapped_b);
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else if (cell->type == "$_ORNOT_")
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map_signal(sig_y, G(ORNOT), mapped_a, mapped_b);
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else
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log_abort();
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module->remove(cell);
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return;
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}
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if (cell->type == "$_MUX_")
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{
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RTLIL::SigSpec sig_a = cell->getPort("\\A");
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RTLIL::SigSpec sig_b = cell->getPort("\\B");
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RTLIL::SigSpec sig_s = cell->getPort("\\S");
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RTLIL::SigSpec sig_y = cell->getPort("\\Y");
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assign_map.apply(sig_a);
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assign_map.apply(sig_b);
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assign_map.apply(sig_s);
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assign_map.apply(sig_y);
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int mapped_a = map_signal(sig_a);
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int mapped_b = map_signal(sig_b);
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int mapped_s = map_signal(sig_s);
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map_signal(sig_y, G(MUX), mapped_a, mapped_b, mapped_s);
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module->remove(cell);
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return;
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}
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if (cell->type.in("$_AOI3_", "$_OAI3_"))
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{
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RTLIL::SigSpec sig_a = cell->getPort("\\A");
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RTLIL::SigSpec sig_b = cell->getPort("\\B");
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RTLIL::SigSpec sig_c = cell->getPort("\\C");
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RTLIL::SigSpec sig_y = cell->getPort("\\Y");
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assign_map.apply(sig_a);
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assign_map.apply(sig_b);
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assign_map.apply(sig_c);
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assign_map.apply(sig_y);
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int mapped_a = map_signal(sig_a);
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int mapped_b = map_signal(sig_b);
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int mapped_c = map_signal(sig_c);
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map_signal(sig_y, cell->type == "$_AOI3_" ? G(AOI3) : G(OAI3), mapped_a, mapped_b, mapped_c);
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module->remove(cell);
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return;
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}
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if (cell->type.in("$_AOI4_", "$_OAI4_"))
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{
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RTLIL::SigSpec sig_a = cell->getPort("\\A");
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RTLIL::SigSpec sig_b = cell->getPort("\\B");
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RTLIL::SigSpec sig_c = cell->getPort("\\C");
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RTLIL::SigSpec sig_d = cell->getPort("\\D");
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RTLIL::SigSpec sig_y = cell->getPort("\\Y");
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assign_map.apply(sig_a);
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assign_map.apply(sig_b);
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assign_map.apply(sig_c);
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assign_map.apply(sig_d);
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assign_map.apply(sig_y);
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int mapped_a = map_signal(sig_a);
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int mapped_b = map_signal(sig_b);
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int mapped_c = map_signal(sig_c);
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int mapped_d = map_signal(sig_d);
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map_signal(sig_y, cell->type == "$_AOI4_" ? G(AOI4) : G(OAI4), mapped_a, mapped_b, mapped_c, mapped_d);
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module->remove(cell);
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return;
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}
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}
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std::string remap_name(RTLIL::IdString abc_name)
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{
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std::stringstream sstr;
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@ -334,168 +124,6 @@ std::string remap_name(RTLIL::IdString abc_name)
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return sstr.str();
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}
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void dump_loop_graph(FILE *f, int &nr, std::map<int, std::set<int>> &edges, std::set<int> &workpool, std::vector<int> &in_counts)
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{
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if (f == NULL)
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return;
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log("Dumping loop state graph to slide %d.\n", ++nr);
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fprintf(f, "digraph \"slide%d\" {\n", nr);
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fprintf(f, " label=\"slide%d\";\n", nr);
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fprintf(f, " rankdir=\"TD\";\n");
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std::set<int> nodes;
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for (auto &e : edges) {
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nodes.insert(e.first);
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for (auto n : e.second)
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nodes.insert(n);
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}
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for (auto n : nodes)
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fprintf(f, " n%d [label=\"%s\\nid=%d, count=%d\"%s];\n", n, log_signal(signal_list[n].bit),
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n, in_counts[n], workpool.count(n) ? ", shape=box" : "");
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for (auto &e : edges)
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for (auto n : e.second)
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fprintf(f, " n%d -> n%d;\n", e.first, n);
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fprintf(f, "}\n");
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}
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void handle_loops()
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{
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// http://en.wikipedia.org/wiki/Topological_sorting
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// (Kahn, Arthur B. (1962), "Topological sorting of large networks")
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std::map<int, std::set<int>> edges;
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std::vector<int> in_edges_count(signal_list.size());
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std::set<int> workpool;
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FILE *dot_f = NULL;
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int dot_nr = 0;
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// uncomment for troubleshooting the loop detection code
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// dot_f = fopen("test.dot", "w");
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for (auto &g : signal_list) {
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if (g.type == G(NONE) || g.type == G(FF)) {
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workpool.insert(g.id);
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} else {
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if (g.in1 >= 0) {
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edges[g.in1].insert(g.id);
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in_edges_count[g.id]++;
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}
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if (g.in2 >= 0 && g.in2 != g.in1) {
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edges[g.in2].insert(g.id);
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in_edges_count[g.id]++;
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}
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if (g.in3 >= 0 && g.in3 != g.in2 && g.in3 != g.in1) {
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edges[g.in3].insert(g.id);
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in_edges_count[g.id]++;
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}
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if (g.in4 >= 0 && g.in4 != g.in3 && g.in4 != g.in2 && g.in4 != g.in1) {
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edges[g.in4].insert(g.id);
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in_edges_count[g.id]++;
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}
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}
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}
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dump_loop_graph(dot_f, dot_nr, edges, workpool, in_edges_count);
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while (workpool.size() > 0)
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{
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int id = *workpool.begin();
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workpool.erase(id);
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// log("Removing non-loop node %d from graph: %s\n", id, log_signal(signal_list[id].bit));
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for (int id2 : edges[id]) {
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log_assert(in_edges_count[id2] > 0);
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if (--in_edges_count[id2] == 0)
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workpool.insert(id2);
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}
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edges.erase(id);
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dump_loop_graph(dot_f, dot_nr, edges, workpool, in_edges_count);
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while (workpool.size() == 0)
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{
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if (edges.size() == 0)
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break;
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int id1 = edges.begin()->first;
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for (auto &edge_it : edges) {
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int id2 = edge_it.first;
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RTLIL::Wire *w1 = signal_list[id1].bit.wire;
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RTLIL::Wire *w2 = signal_list[id2].bit.wire;
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if (w1 == NULL)
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id1 = id2;
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else if (w2 == NULL)
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continue;
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else if (w1->name[0] == '$' && w2->name[0] == '\\')
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id1 = id2;
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else if (w1->name[0] == '\\' && w2->name[0] == '$')
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continue;
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else if (edges[id1].size() < edges[id2].size())
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id1 = id2;
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else if (edges[id1].size() > edges[id2].size())
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continue;
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else if (w2->name.str() < w1->name.str())
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id1 = id2;
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}
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if (edges[id1].size() == 0) {
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edges.erase(id1);
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continue;
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}
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log_assert(signal_list[id1].bit.wire != NULL);
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std::stringstream sstr;
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sstr << "$abcloop$" << (autoidx++);
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RTLIL::Wire *wire = module->addWire(sstr.str());
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bool first_line = true;
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for (int id2 : edges[id1]) {
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if (first_line)
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log("Breaking loop using new signal %s: %s -> %s\n", log_signal(RTLIL::SigSpec(wire)),
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log_signal(signal_list[id1].bit), log_signal(signal_list[id2].bit));
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else
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log(" %*s %s -> %s\n", int(strlen(log_signal(RTLIL::SigSpec(wire)))), "",
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log_signal(signal_list[id1].bit), log_signal(signal_list[id2].bit));
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first_line = false;
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}
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int id3 = map_signal(RTLIL::SigSpec(wire));
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signal_list[id1].is_port = true;
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signal_list[id3].is_port = true;
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log_assert(id3 == int(in_edges_count.size()));
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in_edges_count.push_back(0);
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workpool.insert(id3);
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for (int id2 : edges[id1]) {
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if (signal_list[id2].in1 == id1)
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signal_list[id2].in1 = id3;
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if (signal_list[id2].in2 == id1)
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signal_list[id2].in2 = id3;
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if (signal_list[id2].in3 == id1)
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signal_list[id2].in3 = id3;
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if (signal_list[id2].in4 == id1)
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signal_list[id2].in4 = id3;
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}
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edges[id1].swap(edges[id3]);
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module->connect(RTLIL::SigSig(signal_list[id3].bit, signal_list[id1].bit));
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dump_loop_graph(dot_f, dot_nr, edges, workpool, in_edges_count);
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}
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}
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if (dot_f != NULL)
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fclose(dot_f);
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}
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std::string add_echos_to_abc_cmd(std::string str)
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{
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std::string new_str, token;
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@ -675,7 +303,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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log_header(design, "Extracting gate netlist of module `%s' to `%s/input.xaig'..\n",
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module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str());
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std::string abc_script = stringf("&read %s/input.xaig; ", tempdir_name.c_str());
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std::string abc_script = stringf("&read %s/input.xaig; &ps; ", tempdir_name.c_str());
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if (!liberty_file.empty()) {
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abc_script += stringf("read_lib -w %s; ", liberty_file.c_str());
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@ -729,7 +357,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos))
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abc_script = abc_script.substr(0, pos) + lutin_shared + abc_script.substr(pos+3);
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abc_script += stringf("; &write -v %s/output.xaig", tempdir_name.c_str());
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abc_script += stringf("; &ps; &write -v %s/output.xaig", tempdir_name.c_str());
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abc_script = add_echos_to_abc_cmd(abc_script);
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for (size_t i = 0; i+1 < abc_script.size(); i++)
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@ -752,27 +380,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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}
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}
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for (auto c : cells)
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extract_cell(c, keepff);
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for (auto &wire_it : module->wires_) {
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if (wire_it.second->port_id > 0 || wire_it.second->get_bool_attribute("\\keep"))
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mark_port(RTLIL::SigSpec(wire_it.second));
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}
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for (auto &cell_it : module->cells_)
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for (auto &port_it : cell_it.second->connections())
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mark_port(port_it.second);
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if (clk_sig.size() != 0)
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mark_port(clk_sig);
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if (en_sig.size() != 0)
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mark_port(en_sig);
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||||
handle_loops();
|
||||
|
||||
Pass::call(design, stringf("aigmap; write_xaiger %s/input.xaig", tempdir_name.c_str()));
|
||||
Pass::call(design, stringf("aigmap; write_xaiger -map %s/input.symbols %s/input.xaig; ", tempdir_name.c_str(), tempdir_name.c_str()));
|
||||
|
||||
log_push();
|
||||
|
||||
|
|
@ -865,8 +473,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
|
|||
bool builtin_lib = liberty_file.empty();
|
||||
RTLIL::Design *mapped_design = new RTLIL::Design;
|
||||
//parse_blif(mapped_design, ifs, builtin_lib ? "\\DFF" : "\\_dff_", false, sop_mode);
|
||||
AigerReader reader(mapped_design, ifs, "\\netlist", "\\clk");
|
||||
reader.parse_aiger();
|
||||
buffer = stringf("%s/%s", tempdir_name.c_str(), "input.symbols");
|
||||
AigerReader reader(mapped_design, ifs, "\\netlist", "\\clk", buffer, true /* wideports */);
|
||||
reader.parse_xaiger();
|
||||
|
||||
ifs.close();
|
||||
|
||||
|
|
@ -876,7 +485,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
|
|||
log_error("ABC output file does not contain a module `netlist'.\n");
|
||||
for (auto &it : mapped_mod->wires_) {
|
||||
RTLIL::Wire *w = it.second;
|
||||
RTLIL::Wire *wire = module->addWire(remap_name(w->name));
|
||||
RTLIL::Wire *wire = module->addWire(remap_name(w->name), GetSize(w));
|
||||
if (markgroups) wire->attributes["\\abcgroup"] = map_autoidx;
|
||||
design->select(module, wire);
|
||||
}
|
||||
|
|
@ -1079,10 +688,18 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
|
|||
}
|
||||
|
||||
for (auto conn : mapped_mod->connections()) {
|
||||
if (!conn.first.is_fully_const())
|
||||
conn.first = RTLIL::SigSpec(module->wires_[remap_name(conn.first.as_wire()->name)]);
|
||||
if (!conn.second.is_fully_const())
|
||||
conn.second = RTLIL::SigSpec(module->wires_[remap_name(conn.second.as_wire()->name)]);
|
||||
if (!conn.first.is_fully_const()) {
|
||||
auto chunks = conn.first.chunks();
|
||||
for (auto &c : chunks)
|
||||
c.wire = module->wires_[remap_name(c.wire->name)];
|
||||
conn.first = std::move(chunks);
|
||||
}
|
||||
if (!conn.second.is_fully_const() && conn.second.is_wire()) {
|
||||
auto chunks = conn.second.chunks();
|
||||
for (auto &c : chunks)
|
||||
c.wire = module->wires_[remap_name(c.wire->name)];
|
||||
conn.second = std::move(chunks);
|
||||
}
|
||||
module->connect(conn);
|
||||
}
|
||||
|
||||
|
|
@ -1098,23 +715,51 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
|
|||
for (auto &it : cell_stats)
|
||||
log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second);
|
||||
int in_wires = 0, out_wires = 0;
|
||||
for (auto &si : signal_list)
|
||||
if (si.is_port) {
|
||||
char buffer[100];
|
||||
snprintf(buffer, 100, "\\n%d", si.id);
|
||||
//for (auto &si : signal_list)
|
||||
// if (si.is_port) {
|
||||
// char buffer[100];
|
||||
// snprintf(buffer, 100, "\\n%d", si.id);
|
||||
// RTLIL::SigSig conn;
|
||||
// if (si.type != G(NONE)) {
|
||||
// conn.first = si.bit;
|
||||
// conn.second = RTLIL::SigSpec(module->wires_[remap_name(buffer)]);
|
||||
// out_wires++;
|
||||
// } else {
|
||||
// conn.first = RTLIL::SigSpec(module->wires_[remap_name(buffer)]);
|
||||
// conn.second = si.bit;
|
||||
// in_wires++;
|
||||
// }
|
||||
// module->connect(conn);
|
||||
// }
|
||||
|
||||
// FIXME:
|
||||
module->connections_.clear();
|
||||
|
||||
for (auto &it : mapped_mod->wires_) {
|
||||
RTLIL::Wire *w = it.second;
|
||||
if (!w->port_input && !w->port_output)
|
||||
continue;
|
||||
RTLIL::Wire *wire = module->wire(remap_name(w->name));
|
||||
if (w->port_input) {
|
||||
RTLIL::SigSig conn;
|
||||
if (si.type != G(NONE)) {
|
||||
conn.first = si.bit;
|
||||
conn.second = RTLIL::SigSpec(module->wires_[remap_name(buffer)]);
|
||||
out_wires++;
|
||||
} else {
|
||||
conn.first = RTLIL::SigSpec(module->wires_[remap_name(buffer)]);
|
||||
conn.second = si.bit;
|
||||
in_wires++;
|
||||
}
|
||||
conn.first = wire;
|
||||
conn.second = module->wire(w->name);
|
||||
if (conn.second.empty())
|
||||
log_error("Input port %s not found in original module.\n", w->name.c_str());
|
||||
in_wires++;
|
||||
module->connect(conn);
|
||||
}
|
||||
log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
|
||||
else if (w->port_output) {
|
||||
RTLIL::SigSig conn;
|
||||
conn.first = module->wire(w->name);
|
||||
if (conn.first.empty())
|
||||
log_error("Output port %s not found in original module.\n", w->name.c_str());
|
||||
conn.second = wire;
|
||||
out_wires++;
|
||||
module->connect(conn);
|
||||
}
|
||||
}
|
||||
//log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
|
||||
log("ABC RESULTS: input signals: %8d\n", in_wires);
|
||||
log("ABC RESULTS: output signals: %8d\n", out_wires);
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue