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Reorganising documentation
Also changing to furo theme.
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docs/source/getting_started/examples.rst
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docs/source/getting_started/examples.rst
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Example(s)
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----------
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.. _sec:typusecase:
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Typical use case
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~~~~~~~~~~~~~~~~
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The following example script may be used in a synthesis flow to convert the
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behavioural Verilog code from the input file design.v to a gate-level netlist
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synth.v using the cell library described by the Liberty file :
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.. code:: yoscrypt
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:number-lines:
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# read input file to internal representation
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read_verilog design.v
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# convert high-level behavioral parts ("processes") to d-type flip-flops and muxes
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proc
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# perform some simple optimizations
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opt
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# convert high-level memory constructs to d-type flip-flops and multiplexers
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memory
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# perform some simple optimizations
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opt
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# convert design to (logical) gate-level netlists
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techmap
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# perform some simple optimizations
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opt
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# map internal register types to the ones from the cell library
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dfflibmap -liberty cells.lib
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# use ABC to map remaining logic to cells from the cell library
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abc -liberty cells.lib
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# cleanup
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opt
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# write results to output file
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write_verilog synth.v
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A detailed description of the commands available in Yosys can be found in
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:ref:`cmd_ref`.
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docs/source/getting_started/index.rst
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docs/source/getting_started/index.rst
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Getting started with Yosys
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==========================
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.. toctree::
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installation
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scripting_intro
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examples
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docs/source/getting_started/installation.rst
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docs/source/getting_started/installation.rst
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Installation
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------------
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Supported platforms
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~~~~~~~~~~~~~~~~~~~
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Source tree and build system
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The Yosys source tree is organized into the following top-level
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directories:
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- | backends/
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| This directory contains a subdirectory for each of the backend modules.
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- | frontends/
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| This directory contains a subdirectory for each of the frontend modules.
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- | kernel/
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| This directory contains all the core functionality of Yosys. This includes
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the functions and definitions for working with the RTLIL data structures
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(rtlil.h and rtlil.cc), the main() function (driver.cc), the internal
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framework for generating log messages (log.h and log.cc), the internal
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framework for registering and calling passes (register.h and register.cc),
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some core commands that are not really passes (select.cc, show.cc, …) and a
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couple of other small utility libraries.
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- | passes/
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| This directory contains a subdirectory for each pass or group of passes.
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For example as of this writing the directory passes/opt/ contains the code
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for seven passes: opt, opt_expr, opt_muxtree, opt_reduce, opt_rmdff,
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opt_rmunused and opt_merge.
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- | techlibs/
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| This directory contains simulation models and standard implementations for
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the cells from the internal cell library.
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- | tests/
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| This directory contains a couple of test cases. Most of the smaller tests
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are executed automatically when make test is called. The larger tests must
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be executed manually. Most of the larger tests require downloading external
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HDL source code and/or external tools. The tests range from comparing
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simulation results of the synthesized design to the original sources to
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logic equivalence checking of entire CPU cores.
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The top-level Makefile includes frontends/\*/Makefile.inc,
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passes/\*/Makefile.inc and backends/\*/Makefile.inc. So when extending Yosys it
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is enough to create a new directory in frontends/, passes/ or backends/ with
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your sources and a Makefile.inc. The Yosys kernel automatically detects all
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commands linked with Yosys. So it is not needed to add additional commands to a
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central list of commands.
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Good starting points for reading example source code to learn how to write
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passes are passes/opt/opt_rmdff.cc and passes/opt/opt_merge.cc.
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See the top-level README file for a quick Getting Started guide and build
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instructions. The Yosys build is based solely on Makefiles.
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Users of the Qt Creator IDE can generate a QT Creator project file using make
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qtcreator. Users of the Eclipse IDE can use the "Makefile Project with Existing
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Code" project type in the Eclipse "New Project" dialog (only available after the
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CDT plugin has been installed) to create an Eclipse project in order to
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programming extensions to Yosys or just browse the Yosys code base.
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docs/source/getting_started/scripting_intro.rst
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docs/source/getting_started/scripting_intro.rst
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Scripting in Yosys
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------------------
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.. TODO: copypaste
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Yosys reads and processes commands from synthesis scripts, command line
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arguments and an interactive command prompt. Yosys commands consist of a command
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name and an optional whitespace separated list of arguments. Commands are
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terminated using the newline character or a semicolon (;). Empty lines and lines
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starting with the hash sign (#) are ignored. See :ref:`sec:typusecase` for an
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example synthesis script.
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The command ``help`` can be used to access the command reference manual.
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Most commands can operate not only on the entire design but also specifically on
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selected parts of the design. For example the command dump will print all
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selected objects in the current design while dump foobar will only print the
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module foobar and dump \* will print the entire design regardless of the current
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selection.
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.. code:: yoscrypt
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dump */t:$add %x:+[A] \*/w:\* %i
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The selection mechanism is very powerful. For example the command above will
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print all wires that are connected to the ``\A`` port of a ``$add`` cell.
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Detailed documentation of the select framework can be found in the command
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reference for the ``select`` command.
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