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verilog_backend: emit sync $print cells with same triggers together

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Sort by PRIORITY, ensuring output order.
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Charlotte 2023-06-28 11:51:32 +10:00 • committed by Marcelina Kościelnicka
parent f9d38253c5
commit 04582f2fb7
5 changed files with 297 additions and 274 deletions
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6
tests/fmt/always_full_tb.v
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@ -1,14 +1,12 @@
module always_full_tb;
reg clk = 0;
wire fin;
always_full uut (.clk(clk), .fin(fin));
always_full uut (.clk(clk));
always begin
#1 clk <= ~clk;
if (fin) $finish;
#1 $finish;
end
endmodule