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Add support for SystemVerilog-style `define to Verilog frontend

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This patch should support things like

  `define foo(a, b = 3, c)   a+b+c

  `foo(1, ,2)

which will evaluate to 1+3+2. It also spots mistakes like

  `foo(1)

(the 3rd argument doesn't have a default value, so a call site is
required to set it).

Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.

Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.

Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
This commit is contained in:
Rupert Swarbrick 2020-03-17 09:34:31 +00:00 • committed by Rupert Swarbrick
parent 4c38895fab
commit 044ca9dde4
11 changed files with 636 additions and 151 deletions
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3
passes/cmds/design.cc
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@ -18,6 +18,7 @@
*/
#include "kernel/yosys.h"
#include "frontends/verilog/preproc.h"
#include "frontends/ast/ast.h"
YOSYS_NAMESPACE_BEGIN
@ -346,7 +347,7 @@ struct DesignPass : public Pass {
delete node;
design->verilog_globals.clear();
design->verilog_defines.clear();
design->verilog_defines->clear();
}
if (!load_name.empty() || pop_mode)