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machxo2: Fix more oversights in machxo2 models. logic.ys test passes.

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William D. Jones 2020-11-17 14:22:44 -05:00 committed by Marcelina Kościelnicka
parent 9cb0bae1b2
commit 044393b990
2 changed files with 6 additions and 2 deletions
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6
techlibs/machxo2/cells_map.v
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@ -8,12 +8,16 @@ module \$lut (A, Y);
wire [3:0] I; wire [3:0] I;
generate generate
if(WIDTH == 2) begin if(WIDTH == 1) begin
assign I = {1'b0, 1'b0, 1'b0, A[0]};
end else if(WIDTH == 2) begin
assign I = {1'b0, 1'b0, A[1], A[0]}; assign I = {1'b0, 1'b0, A[1], A[0]};
end else if(WIDTH == 3) begin end else if(WIDTH == 3) begin
assign I = {1'b0, A[2], A[1], A[0]}; assign I = {1'b0, A[2], A[1], A[0]};
end else if(WIDTH == 4) begin end else if(WIDTH == 4) begin
assign I = {A[3], A[2], A[1], A[0]}; assign I = {A[3], A[2], A[1], A[0]};
end else begin
INVALID_LUT_WIDTH error();
end end
endgenerate endgenerate

2
techlibs/machxo2/cells_sim.v
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@ -42,7 +42,7 @@ module FACADE_FF #(
wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR; wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK; wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
assign srval = (REGSET == "SET") ? 1'b1 : 1'b0; wire srval = (REGSET == "SET") ? 1'b1 : 1'b0;
generate generate
if (SRMODE == "ASYNC") begin if (SRMODE == "ASYNC") begin