mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-10-31 03:32:29 +00:00 
			
		
		
		
	Reformat so it shows up/looks nice when "help $alu" and "help $alu+"
This commit is contained in:
		
							parent
							
								
									acfb672d34
								
							
						
					
					
						commit
						041defc5a6
					
				
					 1 changed files with 34 additions and 25 deletions
				
			
		|  | @ -532,13 +532,17 @@ endmodule | ||||||
| 
 | 
 | ||||||
| // -------------------------------------------------------- | // -------------------------------------------------------- | ||||||
| 
 | 
 | ||||||
| // Lookahead carry unit | //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| | ||||||
| //   A building block dedicated to fast computation of carry-bits | //- | ||||||
| //   used in binary arithmetic operations. By replacing the ripple | //-     $lcu (P, G, CI, CO) | ||||||
| //   carry structure used in full-adder blocks, the more significant | //- | ||||||
| //   bits of the sum can be expected to be computed more quickly. | //- Lookahead carry unit | ||||||
| //   Typically created during `techmap` of $alu cells | //- A building block dedicated to fast computation of carry-bits used in binary | ||||||
| //   (see the "_90_alu" rule in +/techmap.v) | //- arithmetic operations. By replacing the ripple carry structure used in full-adder | ||||||
|  | //- blocks, the more significant  bits of the sum can be expected to be computed more | ||||||
|  | //- quickly. | ||||||
|  | //- Typically created during `techmap` of $alu cells (see the "_90_alu" rule in | ||||||
|  | //- +/techmap.v). | ||||||
| module \$lcu (P, G, CI, CO); | module \$lcu (P, G, CI, CO); | ||||||
| 
 | 
 | ||||||
| parameter WIDTH = 1; | parameter WIDTH = 1; | ||||||
|  | @ -563,12 +567,17 @@ endmodule | ||||||
| 
 | 
 | ||||||
| // -------------------------------------------------------- | // -------------------------------------------------------- | ||||||
| 
 | 
 | ||||||
| // Arithmetic logic unit | //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| | ||||||
| //   A building block supporting both binary addition/subtraction | //- | ||||||
| //   operations, and indirectly, comparison operations. | //-     $alu (A, B, CI, BI, X, Y, CO) | ||||||
| //   Typically created by the `alumacc` pass, which transforms | //- | ||||||
| //   $add, $sub, $lt, $le, $ge, $gt, $eq, $eqx, $ne, $nex | //- Arithmetic logic unit. | ||||||
| //   cells into this $alu cell. | //- A building block supporting both binary addition/subtraction operations, and | ||||||
|  | //- indirectly, comparison operations. | ||||||
|  | //- Typically created by the `alumacc` pass, which transforms: | ||||||
|  | //-   $add, $sub, $lt, $le, $ge, $gt, $eq, $eqx, $ne, $nex | ||||||
|  | //- cells into this $alu cell. | ||||||
|  | //- | ||||||
| module \$alu (A, B, CI, BI, X, Y, CO); | module \$alu (A, B, CI, BI, X, Y, CO); | ||||||
| 
 | 
 | ||||||
| parameter A_SIGNED = 0; | parameter A_SIGNED = 0; | ||||||
|  |  | ||||||
		Loading…
	
	Add table
		Add a link
		
	
		Reference in a new issue