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Resolve multiple dimensions defined in stages with typedef

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Dag Lem 2024-01-01 01:18:00 +01:00 • committed by Zachary Snow
parent e0d3977e19
commit 03f35c3def
2 changed files with 70 additions and 74 deletions
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2
frontends/verilog/verilog_parser.y
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@ -2122,7 +2122,7 @@ typedef_decl:
astbuf1->children.push_back(astbuf2);
if ($5 != NULL) {
if (!astbuf2) {
if (!astbuf2 && !astbuf1->is_custom_type) {
addRange(astbuf1, 0, 0, false);
}
rewriteAsMemoryNode(astbuf1, $5);