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https://github.com/YosysHQ/yosys
synced 2025-04-23 17:15:33 +00:00
Added "test_autotb -n <num_iter>" option
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parent
32a1cc3efd
commit
03ef9a75c6
2 changed files with 32 additions and 11 deletions
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@ -17,12 +17,12 @@
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*
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*/
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#include "kernel/register.h"
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#include "kernel/log.h"
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#include "kernel/yosys.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <time.h>
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#define NUM_ITER 1000
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PRIVATE_NAMESPACE_BEGIN
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static std::string id(std::string internal_id)
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{
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@ -70,7 +70,7 @@ static std::string idy(std::string str1, std::string str2 = std::string(), std::
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return id(str1);
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}
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static void autotest(FILE *f, RTLIL::Design *design)
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static void autotest(FILE *f, RTLIL::Design *design, int num_iter)
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{
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fprintf(f, "module testbench;\n\n");
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@ -79,7 +79,7 @@ static void autotest(FILE *f, RTLIL::Design *design)
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fprintf(f, "reg [31:0] xorshift128_x = 123456789;\n");
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fprintf(f, "reg [31:0] xorshift128_y = 362436069;\n");
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fprintf(f, "reg [31:0] xorshift128_z = 521288629;\n");
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fprintf(f, "reg [31:0] xorshift128_w = 88675123;\n");
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fprintf(f, "reg [31:0] xorshift128_w = %u; // <-- seed value\n", int(time(NULL)));
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fprintf(f, "reg [31:0] xorshift128_t;\n\n");
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fprintf(f, "task xorshift128;\n");
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fprintf(f, "begin\n");
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@ -279,7 +279,7 @@ static void autotest(FILE *f, RTLIL::Design *design)
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fprintf(f, "begin\n");
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fprintf(f, "\t$display(\"#OUT#\\n#OUT# ==== %s ====\");\n", idy(mod->name).c_str());
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fprintf(f, "\t%s;\n", idy(mod->name, "reset").c_str());
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fprintf(f, "\tfor (i=0; i<%d; i=i+1) begin\n", NUM_ITER);
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fprintf(f, "\tfor (i=0; i<%d; i=i+1) begin\n", num_iter);
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fprintf(f, "\t\tif (i %% 20 == 0) %s;\n", idy(mod->name, "print_header").c_str());
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fprintf(f, "\t\t#100; %s;\n", idy(mod->name, "update_data").c_str());
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fprintf(f, "\t\t#100; %s;\n", idy(mod->name, "update_clock").c_str());
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@ -307,7 +307,7 @@ struct TestAutotbBackend : public Backend {
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" test_autotb [filename]\n");
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log(" test_autotb [options] [filename]\n");
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log("\n");
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log("Automatically create primitive verilog test benches for all modules in the\n");
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log("design. The generated testbenches toggle the input pins of the module in\n");
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@ -324,12 +324,30 @@ struct TestAutotbBackend : public Backend {
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log("value after initialization. This can e.g. be used to force a reset signal\n");
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log("low in order to explore more inner states in a state machine.\n");
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log("\n");
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log(" -n <int>\n");
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log(" number of iterations the test bench shuld run (default = 1000)\n");
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log("\n");
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}
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virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
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{
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int num_iter = 1000;
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log_header("Executing TEST_AUTOTB backend (auto-generate pseudo-random test benches).\n");
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extra_args(f, filename, args, 1);
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autotest(f, design);
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int argidx;
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for (argidx = 1; argidx < SIZE(args); argidx++)
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{
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if (args[argidx] == "-n" && argidx+1 < SIZE(args)) {
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num_iter = atoi(args[++argidx].c_str());
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continue;
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}
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break;
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}
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extra_args(f, filename, args, argidx);
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autotest(f, design, num_iter);
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}
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} TestAutotbBackend;
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PRIVATE_NAMESPACE_END
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