mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-31 23:34:57 +00:00
Code Activity

clk2fflogic: Consistently treat async control signals as negative hold.

Browse source 
This fixes some dfflegalize equivalence checks, and breaks others — and
I strongly suspect the others are due to bad support for multiple
async inputs in `proc` (in particular, lack of proper support for
dlatchsr and sketchy circuits on dffsr control inputs).
This commit is contained in:
Marcelina Kościelnicka 2020-07-07 14:22:04 +02:00
parent e9c2c1b717
commit 03e28f7ab4
8 changed files with 81 additions and 87 deletions
Download patch file Download diff file Expand all files Collapse all files

4
tests/techmap/dfflegalize_adff.ys
View file

@ -39,8 +39,8 @@ design -save orig
flatten
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP0_ x
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ x
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ x
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ x
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ x
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ x
# Convert everything to ADFFs.