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Clifford Wolf 2014-02-04 16:51:12 +01:00
parent 7a5f378bae
commit 03d63dd861
9 changed files with 206 additions and 3 deletions
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manual/PRESENTATION_ExSyn/techmap_01.v Normal file
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module test(input [31:0] a, b,
output [31:0] y);
assign y = a + b;
endmodule