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presentation progress

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Clifford Wolf 2014-02-04 16:51:12 +01:00
parent 7a5f378bae
commit 03d63dd861
9 changed files with 206 additions and 3 deletions
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40
manual/PRESENTATION_ExSyn/abc_01_cells.v Normal file
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module BUF(A, Y);
input A;
output Y = A;
endmodule
module NOT(A, Y);
input A;
output Y = ~A;
endmodule
module NAND(A, B, Y);
input A, B;
output Y = ~(A & B);
endmodule
module NOR(A, B, Y);
input A, B;
output Y = ~(A | B);
endmodule
module DFF(C, D, Q);
input C, D;
output reg Q;
always @(posedge C)
Q <= D;
endmodule
module DFFSR(C, D, Q, S, R);
input C, D, S, R;
output reg Q;
always @(posedge C, posedge S, posedge R)
if (S)
Q <= 1'b1;
else if (R)
Q <= 1'b0;
else
Q <= D;
endmodule