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presentation progress

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This commit is contained in:
Clifford Wolf 2014-02-04 16:51:12 +01:00
parent 7a5f378bae
commit 03d63dd861
9 changed files with 206 additions and 3 deletions
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manual/PRESENTATION_ExSyn/abc_01.ys Normal file
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read_verilog abc_01.v
read_verilog -lib abc_01_cells.v
hierarchy -check -top test
proc; opt; techmap
abc -dff -liberty abc_01_cells.lib;;