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Clifford Wolf 2014-02-04 16:51:12 +01:00
parent 7a5f378bae
commit 03d63dd861
9 changed files with 206 additions and 3 deletions
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manual/PRESENTATION_ExSyn/abc_01.v Normal file
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module test(input clk, a, b, c,
output reg y);
reg [2:0] q1, q2;
always @(posedge clk) begin
q1 <= { a, b, c };
q2 <= q1;
y <= ^q2;
end
endmodule