3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 06:03:23 +00:00

Added "techmap -map %{design-name}"

This commit is contained in:
Clifford Wolf 2014-07-29 16:06:27 +02:00
parent 397b00252d
commit 03c96f9ce7
4 changed files with 29 additions and 10 deletions

View file

@ -219,6 +219,11 @@ void RTLIL::Selection::optimize(RTLIL::Design *design)
}
}
RTLIL::Design::Design()
{
refcount_modules_ = 0;
}
RTLIL::Design::~Design()
{
for (auto it = modules_.begin(); it != modules_.end(); it++)