Add 'cinput' and 'coutput' to symbols file for boxes

backends/aiger/xaiger.cc

@@ -49,7 +49,8 @@ struct XAigerWriter
 	dict<SigBit, SigBit> not_map, ff_map, alias_map;
 	dict<SigBit, pair<SigBit, SigBit>> and_map;
 	//pool<SigBit> initstate_bits;
-	vector<std::pair<SigBit,int>> ci_bits, co_bits;
+	vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int>> ci_bits;
+	vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int,int>> co_bits;
 
 	vector<pair<int, int>> aig_gates;
 	vector<int> aig_latchin, aig_latchinit, aig_outputs;
@@ -327,6 +328,7 @@ struct XAigerWriter
 				// Box ordering is alphabetical
 				cell->connections_.sort(RTLIL::sort_by_id_str());
 				for (const auto &c : cell->connections()) {
+					int offset = 0;
 					for (auto b : c.second.bits()) {
 						auto is_input = cell->input(c.first);
 						auto is_output = cell->output(c.first);
@@ -335,11 +337,11 @@ struct XAigerWriter
 							SigBit I = sigmap(b);
 							if (I != b)
 								alias_map[b] = I;
-							co_bits.emplace_back(b, 0);
+							co_bits.emplace_back(b, cell, c.first, offset++, 0);
 						}
 						if (is_output) {
 							SigBit O = sigmap(b);
-							ci_bits.emplace_back(O, 0);
+							ci_bits.emplace_back(O, cell, c.first, offset++);
 						}
 					}
 				}
@@ -380,7 +382,7 @@ struct XAigerWriter
 		// Do some CI/CO post-processing:
 		// CIs cannot be undriven
 		for (const auto &c : ci_bits)
-			undriven_bits.erase(c.first);
+			undriven_bits.erase(std::get<0>(c));
 		// Erase all POs that are undriven
 		if (!holes_mode)
 			for (auto bit : undriven_bits)
@@ -399,18 +401,13 @@ struct XAigerWriter
 
 		init_map.sort();
 		if (holes_mode) {
-#ifndef NDEBUG
+			struct sort_by_port_id {
-			RTLIL::SigBit last_bit;
+				bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
-			for (auto bit : input_bits) {
+					return a.wire->port_id < b.wire->port_id;
-				log_assert(!last_bit.wire || last_bit.wire->port_id < bit.wire->port_id);
+				}
-				last_bit = bit;
+			};
-			}
+			input_bits.sort(sort_by_port_id());
-			last_bit = RTLIL::SigBit();
+			output_bits.sort(sort_by_port_id());
-			for (auto bit : output_bits) {
-				log_assert(!last_bit.wire || last_bit.wire->port_id < bit.wire->port_id);
-				last_bit = bit;
-			}
-#endif
 		}
 		else {
 			input_bits.sort();
@@ -431,8 +428,7 @@ struct XAigerWriter
 
 		for (auto &c : ci_bits) {
 			aig_m++, aig_i++;
-			c.second = 2*aig_m;
+			aig_map[std::get<0>(c)] = 2*aig_m;
-			aig_map[c.first] = c.second;
 		}
 
 		if (imode && input_bits.empty()) {
@@ -496,9 +492,9 @@ struct XAigerWriter
 		//	aig_latchin.push_back(1);
 
 		for (auto &c : co_bits) {
-			RTLIL::SigBit bit = c.first;
+			RTLIL::SigBit bit = std::get<0>(c);
-			c.second = aig_o++;
+			std::get<4>(c) = aig_o++;
-			ordered_outputs[bit] = c.second;
+			ordered_outputs[bit] = std::get<4>(c);
 			aig_outputs.push_back(bit2aig(bit));
 		}
 
@@ -774,8 +770,7 @@ struct XAigerWriter
 				//Pass::call(holes_module->design, "techmap");
 
 				Pass::call(holes_module->design, "aigmap");
-				//TODO: clean will mess up port_ids
+				Pass::call(holes_module->design, "clean -purge");
-				//Pass::call(holes_module->design, "clean -purge");
 
 				holes_module->design->selection_stack.pop_back();
 
@@ -880,22 +875,17 @@ struct XAigerWriter
 		}
 
 		for (const auto &c : ci_bits) {
-			RTLIL::SigBit b = c.first;
+			RTLIL::SigBit b = std::get<0>(c);
-			RTLIL::Wire *wire = b.wire;
+			int i = std::get<3>(c);
-			int i = b.offset;
 			int a = bit2aig(b);
 			log_assert((a & 1) == 0);
-			input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
+			input_lines[a] += stringf("cinput %d %d %s %s\n", (a >> 1)-1, i, log_id(std::get<1>(c)), log_id(std::get<2>(c)));
 		}
 
 		for (const auto &c : co_bits) {
-			RTLIL::SigBit b = c.first;
+			int i = std::get<3>(c);
-			RTLIL::Wire *wire = b.wire;
+			int o = std::get<4>(c);
-			int o = c.second;
+			output_lines[o] += stringf("coutput %d %d %s %s\n", o, i, log_id(std::get<1>(c)), log_id(std::get<2>(c)));
-			if (wire)
-				output_lines[o] += stringf("output %d %d %s\n", o, b.offset, log_id(wire));
-			else
-				output_lines[o] += stringf("output %d %d __const%d__\n", o, 0, b.data);
 		}
 
 		input_lines.sort();

frontends/aiger/aigerparse.cc

@@ -704,6 +704,41 @@ void AigerReader::post_process()
                     }
                 }
             }
+            else if (type == "cinput" || type == "coutput") {
+                RTLIL::Wire* wire;
+                if (type == "cinput") {
+                    log_assert(static_cast<unsigned>(variable) < inputs.size());
+                    wire = inputs[variable];
+                    log_assert(wire);
+                    log_assert(wire->port_input);
+                }
+                else if (type == "coutput") {
+                    log_assert(static_cast<unsigned>(variable) < outputs.size());
+                    wire = outputs[variable];
+                    log_assert(wire);
+                    log_assert(wire->port_output);
+                }
+                else log_abort();
+
+                std::string port;
+                mf >> port;
+                RTLIL::IdString cell_name = RTLIL::escape_id(symbol);
+                RTLIL::IdString cell_port = RTLIL::escape_id(port);
+
+                RTLIL::Cell* cell = module->cell(cell_name);
+                if (!cell)
+                    cell = module->addCell(cell_name, "$__blackbox__");
+                wire->port_input = false;
+                wire->port_output = false;
+                if (cell->hasPort(cell_port)) {
+                    log_assert(index == GetSize(cell->getPort(cell_port)));
+                    cell->connections_[cell_port].append(wire);
+                }
+                else {
+                    log_assert(index == 0);
+                    cell->setPort(cell_port, wire);
+                }
+            }
             else
                 log_error("Symbol type '%s' not recognised.\n", type.c_str());
         }

passes/techmap/abc9.cc

@@ -786,14 +786,24 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 				continue;
 			}
 
-			if (c->type == "$lut" && GetSize(c->getPort("\\A")) == 1 && c->getParam("\\LUT").as_int() == 2) {
+			RTLIL::Cell* cell;
-				SigSpec my_a = module->wires_[remap_name(c->getPort("\\A").as_wire()->name)];
+			if (c->type == "$lut") {
-				SigSpec my_y = module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)];
+				if (GetSize(c->getPort("\\A")) == 1 && c->getParam("\\LUT").as_int() == 2) {
-				module->connect(my_y, my_a);
+					SigSpec my_a = module->wires_[remap_name(c->getPort("\\A").as_wire()->name)];
-				continue;
+					SigSpec my_y = module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)];
+					module->connect(my_y, my_a);
+					continue;
+				}
+				else {
+					cell = module->addCell(remap_name(c->name), c->type);
+				}
+			}
+			else {
+				cell = module->cell(c->name);
+				log_assert(cell);
+				log_assert(c->type == "$__blackbox__");
 			}
 
-			RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type);
 			if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
 			cell->parameters = c->parameters;
 			for (auto &conn : c->connections()) {
@@ -802,7 +812,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 					if (c.width == 0)
 						continue;
 					//log_assert(c.width == 1);
-					c.wire = module->wires_[remap_name(c.wire->name)];
+					if (c.wire)
+						c.wire = module->wires_[remap_name(c.wire->name)];
 					newsig.append(c);
 				}
 				cell->setPort(conn.first, newsig);