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Prevent crashes and diagnostics
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parent
f5f673de0f
commit
0379a8b287
3 changed files with 114 additions and 66 deletions
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@ -84,7 +84,7 @@ struct ActivityProp {
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DutyMap.emplace(bit, duties[i]);
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nbBitsWithActivity++;
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} else {
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log_warning("Zeroing out activity for module: %s, wire: %s, wire_size: %d, activ_size: %ld",
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log_warning("Zeroing out activity for module: %s, wire: %s, wire_size: %d, activ_size: %ld\n",
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module->name.c_str(), wire->name.c_str(), GetSize(sig), activities.size());
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ActivityMap.emplace(bit, "0.0");
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DutyMap.emplace(bit, "0.0");
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@ -107,7 +107,7 @@ struct ActivityProp {
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} else {
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RTLIL::SigSpec sigspec(bit);
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if (!sigspec.is_fully_const()) {
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log_warning("No activity found for : %s/%s/%s", module->name.c_str(), cell->name.c_str(), port_name.c_str());
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log_warning("No activity found for : %s/%s/%s\n", module->name.c_str(), cell->name.c_str(), port_name.c_str());
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}
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// constants have no activity
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cell_ports_activity += port_name + "=" + "0.0 ";
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@ -120,7 +120,7 @@ struct ActivityProp {
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} else {
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RTLIL::SigSpec sigspec(bit);
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if (!sigspec.is_fully_const()) {
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log_warning("No dutycycle found for : %s/%s/%s", module->name.c_str(), cell->name.c_str(), port_name.c_str());
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log_warning("No dutycycle found for : %s/%s/%s\n", module->name.c_str(), cell->name.c_str(), port_name.c_str());
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}
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// constant 1 has duty cycle 1, constant 0 has duty cycle 0
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cell_ports_duty += port_name + "=" + (sigspec.as_bool() ? "1.0" : "0.0") + " ";
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