3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-08 12:11:24 +00:00

Re-created command-reference-manual.tex, copied some doc fixes to online help

This commit is contained in:
Clifford Wolf 2015-08-14 11:27:19 +02:00
parent 84bf862f7c
commit 0350074819
10 changed files with 668 additions and 52 deletions

View file

@ -556,7 +556,7 @@ struct TestCellPass : public Pass {
log(" print additional debug information to the console\n");
log("\n");
log(" -vlog {filename}\n");
log(" create a verilog test bench to test simlib and write_verilog\n");
log(" create a Verilog test bench to test simlib and write_verilog\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design*)