mirror of
https://github.com/YosysHQ/yosys
synced 2025-08-26 04:56:05 +00:00
Re-created command-reference-manual.tex, copied some doc fixes to online help
This commit is contained in:
parent
84bf862f7c
commit
0350074819
10 changed files with 668 additions and 52 deletions
|
@ -310,7 +310,7 @@ struct TestAutotbBackend : public Backend {
|
|||
log("\n");
|
||||
log(" test_autotb [options] [filename]\n");
|
||||
log("\n");
|
||||
log("Automatically create primitive verilog test benches for all modules in the\n");
|
||||
log("Automatically create primitive Verilog test benches for all modules in the\n");
|
||||
log("design. The generated testbenches toggle the input pins of the module in\n");
|
||||
log("a semi-random manner and dumps the resulting output signals.\n");
|
||||
log("\n");
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue