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Re-created command-reference-manual.tex, copied some doc fixes to online help

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This commit is contained in:
Clifford Wolf 2015-08-14 11:27:19 +02:00
parent 84bf862f7c
commit 0350074819
10 changed files with 668 additions and 52 deletions
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2
passes/tests/test_autotb.cc
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@ -310,7 +310,7 @@ struct TestAutotbBackend : public Backend {
log("\n");
log(" test_autotb [options] [filename]\n");
log("\n");
log("Automatically create primitive verilog test benches for all modules in the\n");
log("Automatically create primitive Verilog test benches for all modules in the\n");
log("design. The generated testbenches toggle the input pins of the module in\n");
log("a semi-random manner and dumps the resulting output signals.\n");
log("\n");

2
passes/tests/test_cell.cc
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@ -556,7 +556,7 @@ struct TestCellPass : public Pass {
log(" print additional debug information to the console\n");
log("\n");
log(" -vlog {filename}\n");
log(" create a verilog test bench to test simlib and write_verilog\n");
log(" create a Verilog test bench to test simlib and write_verilog\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design*)