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holes_module to be whitebox

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This commit is contained in:
Eddie Hung 2019-12-30 18:46:22 -08:00
parent 65baefecd3
commit 0317a2b476
1 changed files with 10 additions and 0 deletions
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10
passes/techmap/abc9_ops.cc
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@ -434,6 +434,8 @@ void prep_holes(RTLIL::Module *module)
holes_design->modules_.erase(holes_module->name);
holes_module->design = design;
holes_module->set_bool_attribute(ID::whitebox);
log_pop();
}
@ -480,6 +482,14 @@ struct Abc9PrepPass : public Pass {
extra_args(args, argidx, design);
for (auto mod : design->selected_modules()) {
if (mod->get_blackbox_attribute())
continue;
if (mod->processes.size() > 0) {
log("Skipping module %s as it contains processes.\n", log_id(mod));
continue;
}
if (break_scc_mode)
break_scc(mod);
if (unbreak_scc_mode)