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opt_mem, memory_*: Refuse to operate in presence of processes

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Processes can contain `MemWriteAction` entries which are invisible to
most passes operating on memories but which will be lowered to write
ports later on by `proc_memwr`. For that reason we can get corrupted
RTLIL if we sequence the memory passes before `proc`. Address that by
making the affected memory passes ignore modules with processes.
This commit is contained in:
Martin Povišer 2024-02-23 12:26:47 +01:00
parent 975517b022
commit 030d639201
6 changed files with 20 additions and 1 deletions
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3
passes/memory/memory_collect.cc
View file

@ -39,6 +39,9 @@ struct MemoryCollectPass : public Pass {
log_header(design, "Executing MEMORY_COLLECT pass (generating $mem cells).\n");
extra_args(args, 1, design);
for (auto module : design->selected_modules()) {
if (module->has_processes_warn())
continue;
for (auto &mem : Mem::get_selected_memories(module)) {
if (!mem.packed) {
mem.packed = true;

3
passes/memory/memory_libmap.cc
View file

@ -2229,6 +2229,9 @@ struct MemoryLibMapPass : public Pass {
Library lib = parse_library(lib_files, defines);
for (auto module : design->selected_modules()) {
if (module->has_processes_warn())
continue;
MapWorker worker(module);
auto mems = Mem::get_selected_memories(module);
for (auto &mem : mems)

3
passes/memory/memory_map.cc
View file

@ -493,6 +493,9 @@ struct MemoryMapPass : public Pass {
extra_args(args, argidx, design);
for (auto mod : design->selected_modules()) {
if (mod->has_processes_warn())
continue;
MemoryMapWorker worker(design, mod);
worker.attr_icase = attr_icase;
worker.attributes = attributes;

3
passes/memory/memory_narrow.cc
View file

@ -46,6 +46,9 @@ struct MemoryNarrowPass : public Pass {
extra_args(args, argidx, design);
for (auto module : design->selected_modules()) {
if (module->has_processes_warn())
continue;
for (auto &mem : Mem::get_selected_memories(module))
{
bool wide = false;

6
passes/memory/memory_share.cc
View file

@ -558,8 +558,12 @@ struct MemorySharePass : public Pass {
extra_args(args, argidx, design);
MemoryShareWorker msw(design, flag_widen, flag_sat);
for (auto module : design->selected_modules())
for (auto module : design->selected_modules()) {
if (module->has_processes_warn())
continue;
msw(module);
}
}
} MemorySharePass;

3
passes/opt/opt_mem.cc
View file

@ -52,6 +52,9 @@ struct OptMemPass : public Pass {
int total_count = 0;
for (auto module : design->selected_modules()) {
if (module->has_processes_warn())
continue;
SigMap sigmap(module);
FfInitVals initvals(&sigmap, module);
for (auto &mem : Mem::get_selected_memories(module)) {