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add more tests for bounds attributes, fix attributes appearing in verilog

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This commit is contained in:
N. Engelhardt 2024-12-11 16:11:02 +01:00
parent e91e95f501
commit 03033ab6d4
4 changed files with 259 additions and 16 deletions
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14
tests/verific/bounds.sv Normal file
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@ -0,0 +1,14 @@
module test (
input ia,
output oa,
input [0:0] ib,
output [0:0] ob,
input [3:0] ic,
output [3:0] oc
);
assign oa = ia;
assign ob = ib;
assign oc = ic;
endmodule