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Merge https://github.com/YosysHQ/yosys into read_aiger

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Eddie Hung 2019-03-19 08:52:31 -07:00
commit 02e8dc7ad2
113 changed files with 6374 additions and 802 deletions
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1
tests/asicworld/xfirrtl
View file

@ -6,7 +6,6 @@ code_hdl_models_d_latch_gates.v combinational loop
code_hdl_models_dff_async_reset.v $adff
code_hdl_models_tff_async_reset.v $adff
code_hdl_models_uart.v $adff
code_specman_switch_fabric.v subfield assignment (bits() <= ...)
code_tidbits_asyn_reset.v $adff
code_tidbits_reg_seq_example.v $adff
code_verilog_tutorial_always_example.v empty module

21
tests/opt/opt_ff.v Normal file
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@ -0,0 +1,21 @@
module top(
input clk,
input rst,
input [2:0] a,
output [1:0] b
);
reg [2:0] b_reg;
initial begin
b_reg <= 3'b0;
end
assign b = b_reg[1:0];
always @(posedge clk or posedge rst) begin
if(rst) begin
b_reg <= 3'b0;
end else begin
b_reg <= a;
end
end
endmodule

3
tests/opt/opt_ff.ys Normal file
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@ -0,0 +1,3 @@
read_verilog opt_ff.v
synth_ice40
ice40_unlut

58
tests/simple/generate.v
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@ -90,5 +90,61 @@ generate
endcase
end
endgenerate
endmodule
// ------------------------------------------
module gen_test4(a, b);
input [3:0] a;
output [3:0] b;
genvar i;
generate
for (i=0; i < 3; i=i+1) begin : foo
localparam PREV = i - 1;
wire temp;
if (i == 0)
assign temp = a[0];
else
assign temp = foo[PREV].temp & a[i];
assign b[i] = temp;
end
endgenerate
endmodule
// ------------------------------------------
module gen_test5(input_bits, out);
parameter WIDTH = 256;
parameter CHUNK = 4;
input [WIDTH-1:0] input_bits;
output out;
genvar step, i, j;
generate
for (step = 1; step <= WIDTH; step = step * CHUNK) begin : steps
localparam PREV = step / CHUNK;
localparam DIM = WIDTH / step;
for (i = 0; i < DIM; i = i + 1) begin : outer
localparam LAST_START = i * CHUNK;
for (j = 0; j < CHUNK; j = j + 1) begin : inner
wire temp;
if (step == 1)
assign temp = input_bits[i];
else if (j == 0)
assign temp = steps[PREV].outer[LAST_START].val;
else
assign temp
= steps[step].outer[i].inner[j-1].temp
& steps[PREV].outer[LAST_START + j].val;
end
wire val;
assign val = steps[step].outer[i].inner[CHUNK - 1].temp;
end
end
endgenerate
assign out = steps[WIDTH].outer[0].val;
endmodule

2
tests/simple/hierdefparam.v
View file

@ -1,3 +1,5 @@
`default_nettype none
module hierdefparam_top(input [7:0] A, output [7:0] Y);
generate begin:foo
hierdefparam_a mod_a(.A(A), .Y(Y));

19
tests/simple/task_func.v
View file

@ -120,3 +120,22 @@ module task_func_test04(input [7:0] in, output [7:0] out1, out2, out3, out4);
assign out3 = test3(in);
assign out4 = test4(in);
endmodule
// -------------------------------------------------------------------
// https://github.com/YosysHQ/yosys/issues/857
module task_func_test05(data_in,data_out,clk);
output reg data_out;
input data_in;
input clk;
task myTask;
output out;
input in;
out = in;
endtask
always @(posedge clk) begin
myTask(data_out,data_in);
end
endmodule

2
tests/simple/xfirrtl
View file

@ -1,6 +1,7 @@
# This file contains the names of verilog files to exclude from verilog to FIRRTL regression tests due to known failures.
arraycells.v inst id[0] of
dff_different_styles.v
dff_init.v Initial value not supported
generate.v combinational loop
hierdefparam.v inst id[0] of
i2c_master_tests.v $adff
@ -12,7 +13,6 @@ multiplier.v inst id[0] of
muxtree.v drops modules
omsp_dbg_uart.v $adff
operators.v $pow
paramods.v subfield assignment (bits() <= ...)
partsel.v drops modules
process.v drops modules
realexpr.v drops modules

21
tests/simple_defparam/run-test.sh
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@ -1,21 +0,0 @@
#!/bin/bash
OPTIND=1
seed="" # default to no seed specified
while getopts "S:" opt
do
case "$opt" in
S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
seed="SEED=$arg" ;;
esac
done
shift "$((OPTIND-1))"
# check for Icarus Verilog
if ! which iverilog > /dev/null ; then
echo "$0: Error: Icarus Verilog 'iverilog' not found."
exit 1
fi
cp ../simple/*.v .
exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-B \"-defparam\""

12
tests/tools/autotest.sh
View file

@ -8,7 +8,7 @@ verbose=false
keeprunning=false
makejmode=false
frontend="verilog"
backend_opts="-noattr -noexpr"
backend_opts="-noattr -noexpr -siminit"
autotb_opts=""
include_opts=""
xinclude_opts=""
@ -28,7 +28,7 @@ if [ ! -f $toolsdir/cmp_tbdata -o $toolsdir/cmp_tbdata.c -nt $toolsdir/cmp_tbdat
( set -ex; ${CC:-gcc} -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1
fi
while getopts xmGl:wkjvref:s:p:n:S:I:B:-: opt; do
while getopts xmGl:wkjvref:s:p:n:S:I:-: opt; do
case "$opt" in
x)
use_xsim=true ;;
@ -49,7 +49,7 @@ while getopts xmGl:wkjvref:s:p:n:S:I:B:-: opt; do
r)
backend_opts="$backend_opts -norename" ;;
e)
backend_opts="$( echo " $backend_opts " | sed 's, -noexpr ,,; s,^ ,,; s, $,,;'; )" ;;
backend_opts="$( echo " $backend_opts " | sed 's, -noexpr , ,; s,^ ,,; s, $,,;'; )" ;;
f)
frontend="$OPTARG" ;;
s)
@ -65,8 +65,6 @@ while getopts xmGl:wkjvref:s:p:n:S:I:B:-: opt; do
include_opts="$include_opts -I $OPTARG"
xinclude_opts="$xinclude_opts -i $OPTARG"
minclude_opts="$minclude_opts +incdir+$OPTARG" ;;
B)
backend_opts="$backend_opts $OPTARG" ;;
-)
case "${OPTARG}" in
xfirrtl)
@ -84,7 +82,7 @@ while getopts xmGl:wkjvref:s:p:n:S:I:B:-: opt; do
;;
esac;;
*)
echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] [-B backend_opt] [--xfirrtl FIRRTL test exclude file] [--firrtl2verilog command to generate verilog from firrtl] verilog-files\n" >&2
echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] [--xfirrtl FIRRTL test exclude file] [--firrtl2verilog command to generate verilog from firrtl] verilog-files\n" >&2
exit 1
esac
done
@ -183,7 +181,7 @@ do
if [ -n "$firrtl2verilog" ]; then
if test -z "$xfirrtl" || ! grep "$fn" "$xfirrtl" ; then
"$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep -nordff; proc; opt; memory; opt; fsm; opt -full -fine; pmuxtree" ${bn}_ref.v
$firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v -X verilog
$firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v
test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.fir.v
fi
fi

59
tests/various/hierarchy.sh Normal file
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@ -0,0 +1,59 @@
#!/usr/bin/env bash
# Simple test of hierarchy -auto-top.
set -e
echo -n " TOP first - "
../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module"
read_verilog << EOV
module TOP(a, y);
input a;
output [31:0] y;
aoi12 p [31:0] (a, y);
endmodule
module aoi12(a, y);
input a;
output y;
assign y = ~a;
endmodule
EOV
hierarchy -auto-top
EOY
echo -n " TOP last - "
../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module"
read_verilog << EOV
module aoi12(a, y);
input a;
output y;
assign y = ~a;
endmodule
module TOP(a, y);
input a;
output [31:0] y;
aoi12 foo (a, y);
endmodule
EOV
hierarchy -auto-top
EOY
echo -n " no explicit top - "
../../yosys -s - <<- EOY | grep "Automatically selected noTop as design top module."
read_verilog << EOV
module aoi12(a, y);
input a;
output y;
assign y = ~a;
endmodule
module noTop(a, y);
input a;
output [31:0] y;
endmodule
EOV
hierarchy -auto-top
EOY

10
tests/various/run-test.sh
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@ -1,6 +1,14 @@
#!/bin/bash
#!/usr/bin/env bash
set -e
for x in *.ys; do
echo "Running $x.."
../../yosys -ql ${x%.ys}.log $x
done
# Run any .sh files in this directory (with the exception of the file - run-test.sh
shell_tests=$(echo *.sh | sed -e 's/run-test.sh//')
if [ "$shell_tests" ]; then
for s in $shell_tests; do
echo "Running $s.."
bash $s
done
fi